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sameer120
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Registered: ‎05-01-2019

How to obtain the .prm file from a .mcs file using Vivado Hardware Manager?

Hello,

I am using Artix-7 "XA7A50TCSG325-1Q" FPGA.

I have added Remote Update(Xilinx Quick Boot XAPP1081) Feature to our Design.

During production, we want to make sure the Bit Stream (MSC) file programmed is correct using PRM file.

The issue is we genertate MCS file from Bit File  

write_cfgmem -force -format MCS -size 32 -checksum -interface SPIx4 -loadbit "up 0x00000000 $PRJ_DIR/design.bit" -file "$MCS_DIR/bit.mcs"

Then we use Perl Script provided by XAPP1081 and it generates 2 MCS file as below

Command: xilPerl $script_path/MakeSpiFlashProgrammerMcsFiles.pl -imagesize 32 $MCS_DIR/design.mcs

1. design_initial.mcs 

2. design_full_update.mcs

Now our Production team will program the "design_initial.mcs" in SPI Flash using Vivado Hardware Manager, but they want to veryif Check SUM to make sure Programming is Successfull, So for that we need to have design.PRM file

As we generated design_initial.mcs file from Script we are not able to generate correcponding PRM file. I would like to know the way we can generate design.PRM file from design_initial.mcs (MCS File)

Please provide me the Tool command or Script to generate PRM file.

Thansk & Regards

Sameer

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hj
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Registered: ‎06-05-2013

There is no way to generate the checksum from .mcs file if you are using Vivado. Although ISE promgen utility can be useful here. It seems you can use below AR as device in question is Artix 7.
Refer to this AR https://www.xilinx.com/support/answers/33072.html
-Harshit
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sameer120
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Registered: ‎05-01-2019

Hi Harshit,

Thanks for your resonse and confirming that with Vivado its not possible.

If we install ISE Promgen Utility, can we use Vivado BD TCL to call Promgen Utility without manullaly opening the tool? So once we have MCS file generated from Perl Script, we will call the Promgen command to generate .PRM file in automated way.

Thansk

Sameer

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hj
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Registered: ‎06-05-2013

Hi Sameer,
No you cannot invoke ISE from Vivado. You need to perform this manually using ISE.
Thanks
Harshit
-------------------------------------------------------------------------------------
For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
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