04-12-2021 03:16 AM
I designed an IP controller for QSPI Flash memory. I am going to implement my design into Kintex 7 which has a MT25QL128ABA8ESF-0SIT.
In my pin I/O constraint file, I assign my QSPI data (4 pins) and chip select following User Guide table of Kintex 7 as shown below.
But I can not assign my spi_clk pin to FPGA_CCLK (B10 FPGA_CCLK). Vivado said that B10 is an invalid placement site!
Here is my assign pin file.
How can I assign that pin for my design? Does QSPI memory on Kintex 7 support my IP?
04-12-2021 12:28 PM
Vivado has prebuilt Flash Controller files. When you start programming your flash, it automatically gets into action and helps you in programming the flash.
CCLK is in Bank0 of FPGA, which is dedicated bank. User can't control this IO. And this IO has default LVCMOS IO standard.
Hope this helps you.