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minkyo
Visitor
Visitor
219 Views
Registered: ‎03-15-2021

I got ERROR: [Labtools 27-3165] End of startup status: LOW

 

 

Hi 

 

I designed artix7 200t fpga on my own board.

 

when I try simple code to fpga, I got the error. 

 

Property Type Read-only Value
REGISTER.CONFIG_STATUS string true 01000000000000000000111100001100
REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR string true 0
REGISTER.CONFIG_STATUS.BIT01_DECRYPTOR_ENABLE string true 0
REGISTER.CONFIG_STATUS.BIT02_PLL_LOCK_STATUS string true 1
REGISTER.CONFIG_STATUS.BIT03_DCI_MATCH_STATUS string true 1
REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS string true 0
REGISTER.CONFIG_STATUS.BIT05_GTS_CFG_B_STATUS string true 0
REGISTER.CONFIG_STATUS.BIT06_GWE_STATUS string true 0
REGISTER.CONFIG_STATUS.BIT07_GHIGH_STATUS string true 0
REGISTER.CONFIG_STATUS.BIT08_MODE_PIN_M[0] string true 1
REGISTER.CONFIG_STATUS.BIT09_MODE_PIN_M[1] string true 1
REGISTER.CONFIG_STATUS.BIT10_MODE_PIN_M[2] string true 1
REGISTER.CONFIG_STATUS.BIT11_INIT_B_INTERNAL_SIGNAL_STATUS string true 1
REGISTER.CONFIG_STATUS.BIT12_INIT_B_PIN string true 0
REGISTER.CONFIG_STATUS.BIT13_DONE_INTERNAL_SIGNAL_STATUS string true 0
REGISTER.CONFIG_STATUS.BIT14_DONE_PIN string true 0
REGISTER.CONFIG_STATUS.BIT15_IDCODE_ERROR string true 0
REGISTER.CONFIG_STATUS.BIT16_SECURITY_ERROR string true 0
REGISTER.CONFIG_STATUS.BIT17_SYSTEM_MONITOR_OVER-TEMP_ALARM_STATUS string true 0
REGISTER.CONFIG_STATUS.BIT18_CFG_STARTUP_STATE_MACHINE_PHASE string true 000
REGISTER.CONFIG_STATUS.BIT21_RESERVED string true 0000
REGISTER.CONFIG_STATUS.BIT25_CFG_BUS_WIDTH_DETECTION string true 00
REGISTER.CONFIG_STATUS.BIT27_HMAC_ERROR string true 0
REGISTER.CONFIG_STATUS.BIT28_PUDC_B_PIN string true 0
REGISTER.CONFIG_STATUS.BIT29_BAD_PACKET_ERROR string true 0
REGISTER.CONFIG_STATUS.BIT30_CFGBVS_PIN string true 1
REGISTER.CONFIG_STATUS.BIT31_RESERVED string true 0

 

minkyo_0-1625736824080.png

 

This is report property and schemtic what is my problem? 

 

Thanks

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2 Replies
iguo
Xilinx Employee
Xilinx Employee
187 Views
Registered: ‎08-10-2008

By which way did you shift the config data into FPGA? You set mode pins to 111, which means you should have a CPU or something. Or JTAG?

Besides, you don't have strong enough INIT_B pullup, the external INIT_B pin sampled as 0, this will block configuration start.

 

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minkyo
Visitor
Visitor
174 Views
Registered: ‎03-15-2021

Thank you for the answer.

 

Actually, I'm going to use slave serial configuration.

 

But, first I want to test with jtag. 

 

But Jtag doesn't work. 

 

Thanks

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