We are trying to port the xapp1292 project to the VCU128 platform. In the process, we noticed that xapp1292 was originally running on a 7 series FPGA, and the AXI-HWICAP configuration of the engineering group included the STARTUPE2 primitive. On the VCU128 platform, in the VIVADO2019.1 we used, we did not see how to include the STARTUPE primitive (it is recommended in the IP core manual to signal the eos port).
How to use HWICAP correctly on platforms like Ultrascale+? What kind of changes do we need to make from the upgrade of the old 7-series platform?