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mellis
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Registered: ‎12-02-2010

ICAPE2 documentation

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I have an Artix-7 design and I am looking for documentation for the ICAPE2 primitive.  Everything I've found so far appears to be tribal folklore instead of solid documentation.  What would be useful is some basic timing diagrams for reads and writes and how to transition between the two states.  My design uses a Picoblaze to control the ICAPE2.

 

Thanks,

 

Michael

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mellis
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Registered: ‎12-02-2010

Athandr,

 

By digging around online I found that the 7-series ICAPE2 has a fixed 3 cycle latency for reads.

http://www.xilinx.com/support/answers/44942.htm

 

Using this information I modified my design as follows (changes on step 14):

 

1) Enable is negated, rdwr = read, data = FFFFFFFF (negate enable)

2) Enable is negated, rdwr = write, data = FFFFFFFF (change to write mode while not enabled)

3) Enable is asserted, rdwr == write, data = FFFFFFFF (write dummy word)

4) Enable is asserted, rdwr == write, data = 000000BB (write Bus Width Sync Word)

5) Enable is asserted, rdwr == write, data = 11220044 (write Bus Width Detect pattern)

6) Enable is asserted, rdwr == write, data = FFFFFFFF (write dummy word)

7) Enable is asserted, rdwr == write, data = AA995566 (write Sync word)

8) Enable is asserted, rdwr == write, data = 20000000 (write noop)

9) Enable is asserted, rdwr == write, data = 28018001 (write Type1, Read, register IDCODE, count = 1)

10) Enable is asserted, rdwr == write, data = 20000000 (write noop)

11) Enable is asserted, rdwr == write, data = 20000000 (write noop)

12) Enable is negated, rdwr == write, data = 20000000 (negate enable)

13) Enable is negated, rdwr == read, data = 20000000 (change to read mode while not enabled)

14a) Enable is asserted, rdwr == read, data = 20000000 (dummy read cycle - invalid data is read from ICAP - FFFFFFDB)

14b) Enable is asserted, rdwr == read, data = 20000000 (dummy read cycle - invalid data is read from ICAP - 00000000)

14c) Enable is asserted, rdwr == read, data = 20000000 (actual read cycle - valid data is read from ICAP - 13632093)

15) Enable is negated, rdwr == read, data = 20000000 (negate enable)

16) Enable is negated, rdwr == write, data = 20000000 (change to write mode while not enabled)

17) Enable is asserted, rdwr == write, data = 30008001 (write Type 1, write, register CMD, count = 1)

18) Enable is asserted, rdwr == write, data = 0000000D (desync command)

19) Enable is asserted, rdwr == write, data = 20000000 (write noop)

20) Enable is asserted, rdwr == write, data = 20000000 (write noop)

21) Enable is negated, rdwr == write, data = 20000000 (negate enable)

 

With this sequence I am able to read configuration registers.  I appreciate your help and I thank you for the additional material you provided.  I think Xilinx could make our jobs easier by providing more detail regarding ICAP in the Configuration User Guide (UG470) along with the existing multiboot/IPROG information.  There's a lot of good information there but not quite enough to get the job done.  I am using a Picoblaze to talk to the ICAP in my design so detailed timing information for reads, writes and transitions between the two states (to prevent aborts) would be very useful.

 

Thanks,

Michael

 

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mellis
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Registered: ‎12-02-2010

Thanks, I will take a look.

 

Michael

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mellis
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Registered: ‎12-02-2010

Very useful information but I'm still missing something.  I have attached a captured waveform file that shows my ICAP signals but something is still off.

 

Counting each of the clock cycles, I see the following in this file:

 

1) Enable is negated, rdwr = read, data = FFFFFFFF (negate enable)

2) Enable is negated, rdwr = write, data = FFFFFFFF (change to write mode while not enabled)

3) Enable is asserted, rdwr == write, data = FFFFFFFF (write dummy word)

4) Enable is asserted, rdwr == write, data = 000000BB (write Bus Width Sync Word)

5) Enable is asserted, rdwr == write, data = 11220044 (write Bus Width Detect pattern)

6) Enable is asserted, rdwr == write, data = FFFFFFFF (write dummy word)

7) Enable is asserted, rdwr == write, data = AA995566 (write Sync word)

8) Enable is asserted, rdwr == write, data = 20000000 (write noop)

9) Enable is asserted, rdwr == write, data = 28018001 (write Type1, Read, register IDCODE, count = 1)

10) Enable is asserted, rdwr == write, data = 20000000 (write noop)

11) Enable is asserted, rdwr == write, data = 20000000 (write noop)

12) Enable is negated, rdwr == write, data = 20000000 (negate enable)

13) Enable is negated, rdwr == read, data = 20000000 (change to read mode while not enabled)

14) Enable is asserted, rdwr == read, data = 20000000 (actual read cycle - invalid data is read from ICAP - FFFFFFDB)

15) Enable is negated, rdwr == read, data = 20000000 (negate enable)

16) Enable is negated, rdwr == write, data = 20000000 (change to write mode while not enabled)

17) Enable is asserted, rdwr == write, data = 30008001 (write Type 1, write, register CMD, count = 1)

18) Enable is asserted, rdwr == write, data = 0000000D (desync command)

19) Enable is asserted, rdwr == write, data = 20000000 (write noop)

20) Enable is asserted, rdwr == write, data = 20000000 (write noop)

21) Enable is negated, rdwr == write, data = 20000000 (negate enable)

...

Data out of the ICAP actually changes to 00000000 on clock cycle 15 and to 13632093 on clock cycle 16.

 

What am I doing wrong here?  I have bit swapped each individual byte on icap_din and icap_dout.  What is shown here is the unswapped version of the signals.

 

Michael

 

athandr
Xilinx Employee
Xilinx Employee
16,271 Views
Registered: ‎07-31-2012

Hi,

 

There is design of multiboot with ICAEP2 with the AC701 Evaluation kit. Please have a look at the PDF and use the design files for your exact part name. This should give you an idea about the usage of  ICAPE2.

 

PDF - LINK

Design - link

Thanks,
Anirudh

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mellis
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Registered: ‎12-02-2010

Athandr,

 

By digging around online I found that the 7-series ICAPE2 has a fixed 3 cycle latency for reads.

http://www.xilinx.com/support/answers/44942.htm

 

Using this information I modified my design as follows (changes on step 14):

 

1) Enable is negated, rdwr = read, data = FFFFFFFF (negate enable)

2) Enable is negated, rdwr = write, data = FFFFFFFF (change to write mode while not enabled)

3) Enable is asserted, rdwr == write, data = FFFFFFFF (write dummy word)

4) Enable is asserted, rdwr == write, data = 000000BB (write Bus Width Sync Word)

5) Enable is asserted, rdwr == write, data = 11220044 (write Bus Width Detect pattern)

6) Enable is asserted, rdwr == write, data = FFFFFFFF (write dummy word)

7) Enable is asserted, rdwr == write, data = AA995566 (write Sync word)

8) Enable is asserted, rdwr == write, data = 20000000 (write noop)

9) Enable is asserted, rdwr == write, data = 28018001 (write Type1, Read, register IDCODE, count = 1)

10) Enable is asserted, rdwr == write, data = 20000000 (write noop)

11) Enable is asserted, rdwr == write, data = 20000000 (write noop)

12) Enable is negated, rdwr == write, data = 20000000 (negate enable)

13) Enable is negated, rdwr == read, data = 20000000 (change to read mode while not enabled)

14a) Enable is asserted, rdwr == read, data = 20000000 (dummy read cycle - invalid data is read from ICAP - FFFFFFDB)

14b) Enable is asserted, rdwr == read, data = 20000000 (dummy read cycle - invalid data is read from ICAP - 00000000)

14c) Enable is asserted, rdwr == read, data = 20000000 (actual read cycle - valid data is read from ICAP - 13632093)

15) Enable is negated, rdwr == read, data = 20000000 (negate enable)

16) Enable is negated, rdwr == write, data = 20000000 (change to write mode while not enabled)

17) Enable is asserted, rdwr == write, data = 30008001 (write Type 1, write, register CMD, count = 1)

18) Enable is asserted, rdwr == write, data = 0000000D (desync command)

19) Enable is asserted, rdwr == write, data = 20000000 (write noop)

20) Enable is asserted, rdwr == write, data = 20000000 (write noop)

21) Enable is negated, rdwr == write, data = 20000000 (negate enable)

 

With this sequence I am able to read configuration registers.  I appreciate your help and I thank you for the additional material you provided.  I think Xilinx could make our jobs easier by providing more detail regarding ICAP in the Configuration User Guide (UG470) along with the existing multiboot/IPROG information.  There's a lot of good information there but not quite enough to get the job done.  I am using a Picoblaze to talk to the ICAP in my design so detailed timing information for reads, writes and transitions between the two states (to prevent aborts) would be very useful.

 

Thanks,

Michael

 

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mellis
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Registered: ‎12-02-2010

The post containing the 7-Series ICAP PowerPoint seems to have disappeared.

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muzaffer
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Registered: ‎03-31-2012
do you still have the link? it's possible that someone didn't like the idea of having that information public. I'd appreciate a copy of the ppt file if you have a copy.
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