10-01-2019 11:54 PM
How do I put the FPGA in reset? Is it possible to put the FPGA in reset by holding down the INIT_B pin?
When INIT_B is low, does it mean that I can configure/program the external flash device and when I release INIT_B (high), the FPGA would read the flash and configure itself?
After programming the Flash then I should pulse PROGRAM_B?
Is this the right sequence:
1. Hold INIT_B low
2. Program flash
3. Release INIT_B
4. Pulse PROGRAM_B low
Please confirm if my understanding is correct and I would appreciate input if I got it wrong.
10-02-2019 01:57 AM
Assumed you have seen this
The FPGA does not as such have a reset.
Once powered up , it is either configured or not configured ( though some app notes call this configuration reset !! )
INIT_B is a bi directional signal of the FPGA.
"INIT_B can externally be held Low during power-up to stall the power-on configuration sequence at the end of the initialization process."
During this time , the IO pins are either puled up or tri state , depending upon the PUDC_B pin.
Do you need the FPGA to be like this whilst you program the prom , or are you programing the prom throught the FPGA , in which case do not hold this pin low.
"Upon completing the FPGA initialization process, INIT_B is released to high-Z at which time an external resistor is expected to pull INIT_B High"
"When PROGRAM_B is pulsed Low, the FPGA configuration is cleared and a new configuration sequence is initiated"
10-02-2019 03:18 PM
Thanks for your reply. I have read the config document.
My current design programs the external flash through the FPGA and everything is working well.
However, in my next revision of design, I wish to have an external processor (possibly a TI TM4Cxxx processor) to program the external flash. While the TM4C processor programs the external flash, I am hoping to put the FPGA in a "reset" state.
10-31-2019 12:09 AM