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dsammel
Adventurer
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Registered: ‎05-12-2014

IPROG command in Slave SelectMAP mode

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Hello, I have an Artix-7 design where the M[2:0] pins have the value "110" (slave SelectMAP mode). A master processor is responsible for configuring the FPGA. In a certain shutdown scenario, I would like the FPGA to clear its own configuration, just as if the master processor had pulsed PROGRAM_B low. My reason for doing this is to return all of the FPGA I/O to the state of high-impedance with internal pull-up resistors (PUDC is tied low) until my system reboots and the master processor can reconfigure the FPGA.

 

I would like to confirm whether I can use the IPROG command, via the ICAPE2 primitive, to cause the FPGA to clear its own configuration, even though it is in slave SelectMAP mode (I understand that IPROG is typically used in master modes). For example, I need to be sure that the FPGA does not drive the CCLK after the IPROG command, because the master processor is always driving that line.

 

Thanks in advance for your help!

 

Best regards,

Dave

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gurupra
Xilinx Employee
Xilinx Employee
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Registered: ‎01-10-2012

Hi @dsammel

 

Yes. Since you are in slave mode, FPGA will wait for the config data to be fed in.

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tenzinc
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Registered: ‎09-18-2014

dsammel,

 

 

I would like to confirm whether I can use the IPROG command, via the ICAPE2 primitive, to cause the FPGA to clear its own configuration, even though it is in slave SelectMAP mode (I understand that IPROG is typically used in master modes). For example, I need to be sure that the FPGA does not drive the CCLK after the IPROG command, because the master processor is always driving that line.

Yes, you should be able to issue an IPROG via the ICAP. There is a whole "IPROG Using ICAP2" under the "IPROG Reconfiguration" section in UG470 page 145. One thing to note is it will just reconfigure itself to the same image it just cleared since you can't do WBSTAR writes in SMAP. Check RS pins for SMAP. There should be no issues with CCLK as long as the mode pins are set to S-SMAP mode.

 

Related Xilinx Documentation:

 

UG470

 

XAPP583

 

Regards,

T

 



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dsammel
Adventurer
Adventurer
1,530 Views
Registered: ‎05-12-2014

Hello @tenzinc, Thank you for your reply. I have tried issuing the IPROG command on my device and it is causing the DONE pin to be deasserted, so this seems to indicate that the FPGA configuration has been cleared, which is what I was hoping for.

 

My follow-up question is concerning this:

 

"One thing to note is it will just reconfigure itself to the same image it just cleared since you can't do WBSTAR writes in SMAP."

 

It won't be able to reconfigure itself at all unless the master processor sends the image again, correct?

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gurupra
Xilinx Employee
Xilinx Employee
2,059 Views
Registered: ‎01-10-2012

Hi @dsammel

 

Yes. Since you are in slave mode, FPGA will wait for the config data to be fed in.

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dsammel
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Registered: ‎05-12-2014
Excellent, thank you very much! Have a great day. -- Dave
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