03-15-2018 11:39 AM
When BitGen is used in ISE and the Disable_Jtag option is used, what exactly does this do?
In the Xilinx Command Line Tools User Guide (UG629), it states " Disables communication to the Boundary Scan (BSCAN) block via JTAG after configuration."
- Is all JTAG usage disabled or just access to the BSCAN?
- Can JTAG still be used to view inside the FPGA device (i.e. read Control register, read eFUSE settings, etc.)?
- Does the FPGA behave normally other than the BSCAN access through JTAG is turned off, i.e. I/O's behave normally, internal functionality behaves normally, etc.?
03-22-2018 12:02 AM