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Visitor
Visitor
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Registered: ‎03-15-2018

ISE BitGen Command and Disable_JTAG

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When BitGen is used in ISE and the Disable_Jtag option is used, what exactly does this do?

In the Xilinx Command Line Tools User Guide (UG629), it states " Disables communication to the Boundary Scan (BSCAN) block via JTAG after configuration."

 

- Is all JTAG usage disabled or just access to the BSCAN?

- Can JTAG still be used to view inside the FPGA device (i.e. read Control register, read eFUSE settings, etc.)?

- Does the FPGA behave normally other than the BSCAN access through JTAG is turned off, i.e. I/O's behave normally, internal functionality behaves normally, etc.?

 

 

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Visitor
Visitor
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Registered: ‎03-15-2018

Thank you Ivy!

 

-Mike

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008
Disable JTAG will shut down JTAG ports. You cannot run any operations that require JTAG ports, including eFUSE, programming, etc.

Other function of FPGA won't be affected.

Regards,
Ivy
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Visitor
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Registered: ‎03-15-2018

Thank you Ivy!

 

-Mike

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