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Newbie
Newbie
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Registered: ‎10-23-2020

Input pins left unconnected

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Hi,

I'm using an FPGA to control a sensor (providing input data to the FPGA). I would like to run the FPGA with same program .bit file with the sensor unconnected without changing the .xdc and Verilog HDL (i.e. leaving the FPGA input pins floating). If the pins are not driven but are still programmed as LVCMOS33 inputs ports what will the state of those input ports be assigned to in the FPGA? Pretty sure the FPGA will pull unconnected input signals to 0 as I'm seeing from running this scenario. Just checking if that is the expected outcome.

Thanks.

Francesco

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Teacher
Teacher
446 Views
Registered: ‎07-09-2009
What is the FPGA ?
some of the range I think by default have input hold circuits on the pins,
which is a very week pull up / down,

As @bruce_karaffa says, you can also explicitly add a pull up in the VHDL of the FPGA , and on some FPGAs I think a pull down.

If your input if LVCMOS, and the pins are connected to a short track ( say 5 cm or less ) then its going to be "almost" impossible to induce a voltage that's in the middle zone to make the input appear to oscillate. If it was LVDS , then that would be different.

A suggestion, if your worried, when the sensor is not connected, could you connect a short to ground to the inputs ?

BTW: input with out a pull up / down on, you have no guarantee that it will be a '1' or a '0' , as its not defined, so best not to rely upon it being '0' in your code, just in case the next spin of silicon has the opposite as a floating default.



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Registered: ‎06-21-2017

The state of the input will be undefined.  The FPGA may see the input as a low, it may not, or it may oscillate.  You can add a PULLUP or PULLDOWN attribute to the pin and pull an unconnected pin to either logic level.  See the Select IO User Guide for the FPGA family you are using.

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Highlighted
Teacher
Teacher
447 Views
Registered: ‎07-09-2009
What is the FPGA ?
some of the range I think by default have input hold circuits on the pins,
which is a very week pull up / down,

As @bruce_karaffa says, you can also explicitly add a pull up in the VHDL of the FPGA , and on some FPGAs I think a pull down.

If your input if LVCMOS, and the pins are connected to a short track ( say 5 cm or less ) then its going to be "almost" impossible to induce a voltage that's in the middle zone to make the input appear to oscillate. If it was LVDS , then that would be different.

A suggestion, if your worried, when the sensor is not connected, could you connect a short to ground to the inputs ?

BTW: input with out a pull up / down on, you have no guarantee that it will be a '1' or a '0' , as its not defined, so best not to rely upon it being '0' in your code, just in case the next spin of silicon has the opposite as a floating default.



<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

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Newbie
Newbie
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Registered: ‎10-23-2020

@drjohnsmith and @bruce_karaffa thanks for your replies. I'm using the 7 series. As @drjohnsmith pointed out there is a weak pull-down by default which is pulling down undriven input pins. This is consistent with the output I'm seeing from the FPGA. Took a bit of searching through xilinx manuals but finally found the default hold circuit. Thanks.