07-06-2021 04:24 AM
I have read the Xilinx radiation test report summary on the XQRKU060. The document lists the SEU rates for a number of test designs, such as a counters and windowed shift-registers. However, it is not clear how I can translate the rates obtained in this way to likely SEU's on our own design.
Reading "Field Programmable Gate Array (FPGA) Single Event Effect (SEE) Radiation Testing" by M. Berg clarifies why these structures are used to get an indication of the radiation hardness of the FPGA's flip-flops. But is it possible to obtain worst-case SEU rates specifically on flip-flops, LUTs and the global clock trees from here?
For the Flip-flops I assume that the amount of errors/design devided by the amount of bits used per design is a worst-case estimation, considering that errors could also come from SET's in CL or events in the global tree. However, the extrapolation for LUTs and the global clock tree is not clear to me.
An understanding of the expected worst-case rates in our design is necessary in order to estimate the scope of the mitigation we need to foresee.
07-08-2021 06:11 AM
Have you taken a look at the Xilinx SEU Estimator?
Would this address everything you are looking for?
You can download the SEU Estimator and supporting documentation from the Xilinx Reliability site upon registration:
07-15-2021 04:24 AM
Thank you for your reply. I had a look at the SEU calculator, and it seems the XQRKU060 is not supported at this time. The environments the sheet seems to support are also not really what I am looking for. To be clear: Our application is a space application. I've already explored the space lounge, but there do not seem to be resources there that answer my questions.