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Observer
Observer
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Registered: ‎05-10-2018

Is is necessary to control PROGRAM_B in normal startup sequence?

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HI, I have a question about startup sequence of Artix-7. In the chart of SPI mode startup sequence in UG470, PROGRAM_B goes High -> Low -> High. I understand reconfiguration is occrred by this action, but is it necessary? Even If I don't control PROGRAM_B, does configuration start automatically after Vcc ramp-up? Now in our system, CPLD drives PROGRAM_B Low from power-on and after Vcc rampup drives High(Low -> High) because I overlooked the caution of PROGRAM_B (=Note: Holding PROGRAM_B Low from power-on does not keep the FPGA configuration in reset.) In case of our system, the action of PROGRAM_B is meaningless, right? As a result, is there no problem of FPGA configuration in our system?
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773 Views
Registered: ‎07-23-2019

"When
PROGRAM_B is pulsed Low, the FPGA configuration is
cleared and a new configuration sequence is initiated"

From UG470. From that I understand if you keep it low it should start the configuration. also note:

Note: Holding PROGRAM_B Low from power-on does not
keep the FPGA configuration in reset

The problem is it may not work when all voltages are ramping up.

What about one of these reset generators for MCUs?  A tiny cheapy 3-lead bit will do that for you

 

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774 Views
Registered: ‎07-23-2019

"When
PROGRAM_B is pulsed Low, the FPGA configuration is
cleared and a new configuration sequence is initiated"

From UG470. From that I understand if you keep it low it should start the configuration. also note:

Note: Holding PROGRAM_B Low from power-on does not
keep the FPGA configuration in reset

The problem is it may not work when all voltages are ramping up.

What about one of these reset generators for MCUs?  A tiny cheapy 3-lead bit will do that for you

 

View solution in original post

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Observer
Observer
746 Views
Registered: ‎05-10-2018

Thank you for your reply!

 

You say 'The problem is it may not work when all voltages are ramping up.'

 

What does this comment mean?

 

Now I attached the waveform of our system. CPLD rises PROGRAM_B, but before that, INIT_B already rises. (CPLD does not drive INIT_B)

So, I thought in our system, PROGRAM_B signal is meaningless and FPGA check the voltage level by itself and decide the timing to start configuration automatically as the chart 'Device Power-Up Timing'.

 

Also, now it's difficult to change our circuit design. So I hope current design has not so much problem. 

 

waveform.png
Device Power-Up Timing.png
SPImode_Seq.png
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Observer
Observer
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Registered: ‎05-10-2018

Sorry, I understand.

"The problem is it may not work when all voltages are ramping up" means that

PROGRAM_B (= reconfiguration function) may work only after all voltages become ready, right?

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Registered: ‎07-23-2019

@s-kaku 

Yes, that's what I meant. As per the UG, I understand configuration is started by level not by edge, so if you tie it low, it may start when other parts are still powering up or setting up. 

But you said a CPLD rises PROGRAM_B. In that case, you could have a delay os some ms in that CPLD before it pulses it low then back high again.

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Teacher
Teacher
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Registered: ‎07-09-2009

Have a look at fig 2.2 here

https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf

This looks like what I imagine is your system , and init_b is an input to the CPLD.

prog_b is the only configuration control output of the CPLD.

The feature, is prog_b has to be pulsed after the power supplies are stable.

So if your circuit does this, then all is happy , if it does not, your into a mod .

 

 

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Observer
Observer
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Registered: ‎05-10-2018

Thank you so much, archangel and drjohnsmith.

 

I understand your description. Now, PROGRAM_B is not pulsed after the power supplies are stable in our system...

 

So is it correct that what I have to do is

to check whether FPGA power supply and other parts (especially SPI flash) become ready before INIT_B rise ?

   -> If not, I think I have to change CPLD logic to make pulse after power supplies are stable as you two suggest.

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Teacher
Teacher
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Registered: ‎07-09-2009

have another look at fig 2.2

What do you note about init_b and prog_b regarding timing,

does that answer your question ?

 

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Observer
Observer
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Registered: ‎05-10-2018

Thank you.

 

In our system, INIT_B is not connected to other devices.
So now I plan to make PROGRAM_B pulse after power supplies are stable.

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Teacher
Teacher
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Registered: ‎07-09-2009

@s-kaku 

well doen, let us know how it goes.

That would be a sencible thing to do , and what most other systems I have seen do.

Prog_b is the start of the initalisatoin cycle,

 

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Xilinx Employee
Xilinx Employee
600 Views
Registered: ‎03-07-2018

Hello @s-kaku 

Adding some inputs to @archangel-lightworks inputs,

The device can be reconfigured with toggling the PROGRAM_B pin, cycling power, or issuing the JPROGRAM instruction.

I will recommend to check Figure 10-6: Device Configuration Flow Diagram provided in UG470 (v1.13.1) along with Configuration Sequence details (Page 84 ~92).

Regards,
Bhushan

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Observer
Observer
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Registered: ‎05-10-2018

Thank you, @drjohnsmith and @bpatil .

 

I checked UG470 and start-up sequence of our system.

Then, rise-time of VCCO is too long and it makes whole sequence bad.

So I improve the rise-time by changing RC values, and aiso make PROGRAM_B toggled after all power supply is stable.  Now, the sequence match to UG470.

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Teacher
Teacher
499 Views
Registered: ‎07-09-2009

Veyr good news to hear feedback , great its working.

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