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richardhead
Scholar
Scholar
1,580 Views
Registered: ‎08-01-2012

Is there a standard format for bitfile header?

Is there any standard for the bitfile header? We see that the top level name is written to the header in cleartext, along with a few other fields and things like vivado version, part number etc. Is there a standard for this? can we specify what the top level name written to the bitfile is?

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rshekhaw
Xilinx Employee
Xilinx Employee
1,511 Views
Registered: ‎05-22-2018

Hi @richardhead ,

Which device family are you targeting?

For example for Ultrascale device configuration data file format check page no.139:

https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf

Thanks,

Raj

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hj
Moderator
Moderator
1,428 Views
Registered: ‎06-05-2013

@richardhead

You can generate the .rbt file to see the bitstream header. There are so many factors to it. Like Vivado tool version, date, design top name etc.
There is no specific size to it. Although configuration engine completely ignores that part.

It takes the design top module name as the bitstream name. I have attached the sample header information from rbt file. So you can change the name of top level and generate a new bit file with appropriate name. 

rbt.JPG

If that is not possible you can use USER_ID as the identifier which is also in the header part. Used to identify implementation revisions. You can enter up to an 8-digit hexadecimal string in the User ID register

user_id.JPG

 

If that does not work, you can define USR_ACCESS register in bitstream settings and use it as identifier. This can be read via JTAG. Refer to the following XAPP https://www.xilinx.com/support/documentation/application_notes/xapp1232-bitstream-id-with-usr_access.pdf

Hope it helps. 

Thanks

Harshit 

 
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For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
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