cancel
Showing results for 
Search instead for 
Did you mean: 
Contributor
Contributor
248 Views
Registered: ‎11-06-2018

Issues with .ll and .msk file with an SSI Ultrascale+ chip (VCU118)

Hi all,

 

I'm using a VCU118 board and trying to do readback verify and capture. I'm tryng to use the information from .ll file to find the corresponding bit in the .msk file, as stated in xapp1230.

However, I found in the bitstream files genereated for VCU118:

  1. the register bit in .msk is 0 (static logic) when it's supposed be 1 (dynamic states).
  2. the value in the generated .rba is not correct


I've applied the following steps to other non-SSI chips, all worked. Only the contents in VCU118 files are not expected.

 

FWIW, I will just document the steps I took. If anyone knows anything, please help. Thank you.

 

Overall:

I wrote a simple counter module, the point of interest is the 8 bits counter register. After Generate Bitstream,we got many files, including .ll, .bin, .msk and so on. Next, I will find my counter_reg in the .ll file, then use the bit offset from .ll to calculate the correct word offset, which will be used to find the bit in the .msk file.

 

Environment:

  1. Linux Centos8.
  2. Vivado 2019.2, 2019.1 and 2018.3 all used.
  3. Board: VCU118 with a Ultrascale+ SSI chip.
    1. The bitstream files have 3 parts because there are 3 SSI parts.


Verilog Source Code:

 

module test_counter(
    input clk, input rst_n,
    output reg[31:0] data_out);
   
    reg [7:0] counter = 8'b10101011;
   
    always @ (posedge clk) begin
                counter <= counter + 1;
                data_out <= counter;
    end
endmodule


Generated Files:

 

  1. The .ll file. The information I got: 1) a list of bit offsets. 2) All of them are in SLR1 partition. 3) SLR1 is the first part in the bitstream file.
    1. Bit   57846590 0x0004ee0c 2078 SLR1 0 Block=SLICE_X120Y401 Latch=AQ2 Net=base_mb_i/test_counter_0/U0/counter_reg[0]
      Bit   57846592 0x0004ee0c 2080 SLR1 0 Block=SLICE_X120Y401 Latch=BQ2 Net=base_mb_i/test_counter_0/U0/counter_reg[1]
      Bit   57846596 0x0004ee0c 2084 SLR1 0 Block=SLICE_X120Y401 Latch=CQ2 Net=base_mb_i/test_counter_0/U0/counter_reg[2]
      Bit   57846598 0x0004ee0c 2086 SLR1 0 Block=SLICE_X120Y401 Latch=DQ2 Net=base_mb_i/test_counter_0/U0/counter_reg[3]
      Bit   57846614 0x0004ee0c 2102 SLR1 0 Block=SLICE_X120Y401 Latch=EQ2 Net=base_mb_i/test_counter_0/U0/counter_reg[4]
      Bit   57846616 0x0004ee0c 2104 SLR1 0 Block=SLICE_X120Y401 Latch=FQ2 Net=base_mb_i/test_counter_0/U0/counter_reg[5]
      Bit   57846620 0x0004ee0c 2108 SLR1 0 Block=SLICE_X120Y401 Latch=GQ2 Net=base_mb_i/test_counter_0/U0/counter_reg[6]
      Bit   57846622 0x0004ee0c 2110 SLR1 0 Block=SLICE_X120Y401 Latch=HQ2 Net=base_mb_i/test_counter_0/U0/counter_reg[7]
  2. Calculate the word offsets from the above bit offset.
    1.                  BitOffset      BitOffset/32           BitOffset%32
                                      (Word Offset)        (Within a word)
      counter_reg[0]   57846590	1807705	              30
      counter_reg[1]   57846592	1807706                0
      counter_reg[2]   57846596	1807706	               4
      counter_reg[3]   57846598	1807706	               6
      counter_reg[4]   57846614	1807706	              22
      counter_reg[5]   57846616	1807706	              24
      counter_reg[6]   57846620	1807706	              28
      counter_reg[7]   57846622	1807706	              30

       

  3. Translate the generated binary .msk file into an ASCII file. Find the FDRI data section, apply the word offset we calculated above.
    1. This is the .msk file.

      Word Offset + Commands + Description [ 93] 30002001 Write to FAR [ 94] 00000000 [ 95] 30008001 Write to CMD [ 96] 00000001 [ 97] 20000000 [ 98] 30004000 Write to FDRI [ 99] 5065eadc [ 100] 00000000 (Start of Data Section or the MASK data) [ 101] 00000000 ... ... [ 1807805] 00000000 (line 1807805 = 100 + 1807705) (counter_reg[0]) [ 1807806] 00000000 (line 1807806 = 100 + 1807706) (counter_reg[1-7) [ 1807807] 00000000
      ...
  4. Since these counter_reg bits are registers, I expect them to be 1, meaning dynamic bits that should not be compared with the readback data. But here is 0. Why? Am I doing something wrong? Or Vivado has a bug in this particular case?
  5. Other than the above, I also checked the .bin file. This is the file to program FPGA. It's all good. Values match.
    1. This is the .bin file.
      
      Word Offset + Commands + Description
      
      [        63] 30002001 Write to FAR
      [        64] 00000000
      [        65] 30008001 Write to CMD
      [        66] 00000001
      [        67] 20000000
      [        68] 30004000 Write to FDRI
      [        69] 5065eadc
      [        70] 00000000        
      [        71] 00000000
      ..
      ..
      [   1807774] 00000000
      [   1807775] 20000000                 (line 1807775 = 70 + 1807705) (counter_reg[0])
      [   1807776] 9a60009a                 (line 1807776 = 70 + 1807706) (counter_reg[1-7)
      [   1807777] 00000000
  6. But, .rba file is wrong.  Is this a bug?
    1. [        77] 28006000 Read from FDRO
      [        78] 4865eadc
      [        79] 00000000
      ..
      [   1807784] 00000000    (Where counter_reg[0] supposed to be.)    79+1807705=1807784
      [   1807785] 00000000    (Where counter_reg[1-6] supposed to be.)  79+1807706=1807785
      ..
      .. (Surpringly, the distance is 93, a frame!)
      .. [ 1807877] 20000000 (Where counter_reg[0] actually is) 1807877-1807784 = 93 [ 1807878] 9a60009a (Where counter_reg[1-6] actually is)
0 Kudos
1 Reply
Highlighted
Visitor
Visitor
169 Views
Registered: ‎08-04-2014

Re: Issues with .ll and .msk file with an SSI Ultrascale+ chip (VCU118)

Not sure whats happening here but i would try to not care about the mask file for capture and simply use the values that i readback from the offset directly. It works for me on my SSI (Virtex7-2000T) device.

Does the offset value you readback match what you expect without applying the mask?

0 Kudos