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346 Views
Registered: ‎12-02-2019

JTAG Issue zynq z7020

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I have set up a custom board with Zynq Z7020 SOC. I am not able to see either Either the FPGA or Arm cores in the Jtag debug software. The board is in Jtag boot mode.

  I'm using diligent HS3 cable and Using xsct software >connect >targets shows up error "DR shift output all zeros").

I have checked the voltage rails of both PS, PL, and PS_POR_B, power sequencing, clock and all seems to be working fine.

What else could be wrong?

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Registered: ‎12-02-2019

Hey

So the issue was that the "vccpll" pin of the Zynq SOC was not powered.

One that design flaw was fixed, the board started working correctly.

 

View solution in original post

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008

Check INIT_B, PROG_B  or DONE pin on the board, see if any of them is grounded.

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Registered: ‎12-02-2019

Hey Iguo,

Thanks for your reply.

I have cross-checked the pins and they seem to be fine.

I am using the automative grade of the Zynq IC, will that require any special change compared to the commercial-grade connections?

Thanks

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Registered: ‎12-02-2019

Hey,

One more issue i noticed is that the Init_b pin, never goes low. (even in qspi flash and sd card boot mode, even if sd card is not present).

Ideally, it should go low when an error occurs right,

I have also attached part of  oscilloscope output (TDO vs TCK), TDO seems to be providing proper output for some part of TCK, but I am still getting the "DR shift output all zeros error).

jtag.png
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Registered: ‎12-02-2019

Hey

So the issue was that the "vccpll" pin of the Zynq SOC was not powered.

One that design flaw was fixed, the board started working correctly.

 

View solution in original post

0 Kudos