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Visitor
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Registered: ‎07-31-2014

JTAG V5 bitfile binary file format

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I am trying to configure one V5 with another V5 using JTAG.  I have written verilog to execute the steps shown in UG191 Table 3-4 and from what I can tell in simulation and from scope probing all those commands are being sent correctly.  However, the FPGA does not get configured, and I am not sure I am sending the bitstream in the right format.  Right now I have tried sending the bitfile in binary format that was generated with this command:

 

promgen -w -p bin -spi -o system.bin -u 0 system.bit

 

I have tried with both bit-swapping and not bit-swapping and neither work.  I am sending the MSB of the file first like it says in UG191.  This bitfile format has worked for me in the past using SelectMAP programming from another FPGA.  Is there some other format I should be using?   I am investigating xsvf right now but it has extra binary at the beginning and end that is not part of the bitfile.

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Visitor
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Registered: ‎07-31-2014

Re: JTAG V5 bitfile binary file format

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It turns out there is a slight typo in UG191.  On Table 3-4, Step 13 TMS should equal 0.  I ended up using the bin file generated from bitgen using the -g binary:yes option.  Done is going high and the FPGA was configured correctly.

 

I am still curious about how I made Done go high incorrectly earlier, I must have been writing a Xilinx reserved command into IR and something strange happened.

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Teacher
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Registered: ‎07-09-2009

Re: JTAG V5 bitfile binary file format

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JTAG does not use SPI , yet your producing the bit file in SPI format.

 

Are you trying to program an spi prom on the second fpga or actually configure the FPGA.

 

 

 

 

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Visitor
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Re: JTAG V5 bitfile binary file format

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I am trying to configure the FPGA.  With bit swapping ( no -spi option) I was able to make the V5 DONE pin on the board go high. The only change to my code was to clock in an extra TMS in steps 1 and 12 in UG191 to make sure the TAP got reset.  However, the FPGA is not operational despite the DONE pin going high.  That makes me think CRC check must have at least worked, but I am not sure at what point in the process shown in Fig. 3-6 DONE goes high.  I think am loading in the CFG_IN instruction correctly if DONE goes high so I assume I am loading JSTART correctly as well.  

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Registered: ‎07-31-2014

Re: JTAG V5 bitfile binary file format

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It appears that the done pin goes high regardless of the bitfile I send, I am not sure what I could be doing to cause that.

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: JTAG V5 bitfile binary file format

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well you've stumped me with that done pin action,

 

can not see how that happens, 

     

have you looked at the other configuration pins ?

    if I remember init_b and program can be monitored to get a clue as to whats happening.

 

check circuit time me thinks, 

   pull ups and such like.

 

on a side note, 

    I'm confused as to why you using jtag to configure one fpga from another ?

        I'd have used slave serial for the second fpga, 

 

Any chance of a circuit of what your doing.

 

 

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Visitor
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Registered: ‎07-31-2014

Re: JTAG V5 bitfile binary file format

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Yes, the done pin going high was quite confusing and gave me a lot of false hope.

I discovered that since I am using an FX130 V5 the instruction register is 14 bits, not 10.  So I was making a mistake there and not giving the TAP the instructions correctly.  Now the current draw of the board jumps up after the JSTART instruction is sent which is a good sign.  Now V5 Done does not go high.  INIT_B stays high for the whole programming sequence, which means no CRC error was detected.

 

I still believe there is something wrong with the format of the configuration file I am using.  It would be nice to use whatever the XSVF file generates but I am not sure how to extract just the bitfile from that.  The lack of CRC error makes me think I am not sending enough bits across.

 

The decision to use JTAG to configure from one FPGA to another was not mine...  Slave serial would have been much better.  The circuit being used works using a normal JTAG header from a computer so I don't think that is the issue. 

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Registered: ‎07-31-2014

Re: JTAG V5 bitfile binary file format

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It turns out there is a slight typo in UG191.  On Table 3-4, Step 13 TMS should equal 0.  I ended up using the bin file generated from bitgen using the -g binary:yes option.  Done is going high and the FPGA was configured correctly.

 

I am still curious about how I made Done go high incorrectly earlier, I must have been writing a Xilinx reserved command into IR and something strange happened.

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