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flob
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Registered: ‎06-19-2019

KCU105 - Vivado 2018.2 vs Vivado 2019.2

Hi,

we have developped a project for the KCU105 with Vivado2018.2.

The design was correct : the bitstream of the FPGA was downloaded in the SPI Flash memory of the KCU105 board. There are communications exchanges between the FPGA and a ASIC through the FMC connector.

We have decided to move to Vivado2019.2 because some other teams have done it. With the same source and constraint files, the behavior of the FPGA is different. The FPGA seems to be unable to program from the SPI memory and the Vadj = 0.8V instead of 1.8V. We need to use the program_b push-button to correctly program the FPGA; when it's done the design works correctly like for the 2018.2 version.

I've cheched the bitstream settings and they seem to be the same for the 2 versions of Vivado.

I use the Linux version of Vivado.

Thanks in advance for your support.

Regards,

Florence

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hj
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Registered: ‎06-05-2013

Can you confirm if the cable is connected while booting from flash? If so disconnect the JTAG cable and see if you see the expected results. https://www.xilinx.com/support/answers/66954.html

-Harshit
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For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
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flob
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Registered: ‎06-19-2019

Hi,

Yes, the cable was connected while booting from the Flash (but it was also the case for the bit file generated with Vivado 2018.2).

Due to the actuel situation, we will be able to test that only by the end of the week. The board is in our lab and we work at home.

I will let you know the results of our test.

Regards,

Florence

 

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flob
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Registered: ‎06-19-2019

Hi,

We did the tests described on the HTML page https://www.xilinx.com/support/answers/66954.html but the result is the same.

With the bitstream generated by Vivado2019.2, the FPGA is not able to boot from the SPI Flash.

The bitstream generated by Vivado2019.2 is 6.3MB and the bitstream generated by Vivado2018.2 is 6.7MB

Regards,

Flo

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hj
Moderator
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288 Views
Registered: ‎06-05-2013

Disconnect the JTAG and let it boot from flash. upon failure connect the JTAG cable and include the status registers and bitstream properties.
-------------------------------------------------------------------------------------
For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
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Don’t forget to reply, kudo, and accept as solution.
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