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Explorer
Explorer
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Registered: ‎09-14-2018

KCU105 .bit and .mcs files for original FPGA image

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Hello,

I have Vivado 2018.3. I need to configure the KCU105 eval board with the original FPGA image. I assumed that the rdf0313-kcu105-ipi-c-2017-3.zip has the right KCU105 project. For a number of reasons, I was not able to re-compile it. I found in folder “ready_for_download” ipi_app.bit file. After attempt to generate .mcs files

write_cfgmem -format MCS -size 32 -interface SPIx8 -loadbit "up 0x0 ipi_app.bit”  ipi_app.mcs

I got the following message:

ERROR: [Writecfgmem 68-24] The SPIX8 interface does not support daisy chaining bit files.

What is wrong with that bit file? Can I get the mcs files for the KCU105 original image?

Thank you.

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Explorer
Explorer
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Registered: ‎09-14-2018

Hi Deepak,

I have found out why I had that error message. In the file path I used back slash (copy fro windows path) instead of regular slash character.

Anyway, the Xilinx error message is very misleading.

Thank you.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-06-2018

Hi @arotenst 

write_cfgmem -format MCS -size 32 -interface SPIx8 -loadbit "up 0x0 ipi_app.bit”  ipi_app.mcs

I got the following message:

ERROR: [Writecfgmem 68-24] The SPIX8 interface does not support daisy chaining bit files.

 

>>> Your MCS File generation Command is incorrect.

I tried generating SPIx8 MCS file for KCU105 Board and was successful. Please use this command as reference : write_cfgmem -format mcs -size 64 -interface SPIx8 -loadbit {up 0x00000000 "./KCU105.bit" } -file "./KCU105SPIx8"

 

Ensure your BIT File XDC has following properties in XDC File, otherwise you will face errors in MCS File generation  : 

set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design];
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design];
set_property CONFIG_MODE SPIx8 [current_design];

 

For KCU105 Board to revert back to Factory settings, please refer KCU105 Flash restoration Steps ( Design files  ) . Design files contains MCS File and Bit File.

Regards,
Deepak D N
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Explorer
Explorer
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Registered: ‎09-14-2018

Hi Deepak,

I have found out why I had that error message. In the file path I used back slash (copy fro windows path) instead of regular slash character.

Anyway, the Xilinx error message is very misleading.

Thank you.

 

View solution in original post

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-14-2014

Hi @arotenst ,

May I know in which command exactly did you use Windows-style path? Because the original command which you've posted is -

write_cfgmem -format MCS -size 32 -interface SPIx8 -loadbit "up 0x0 ipi_app.bit”  ipi_app.mcs

which doesn't have any path to bit file. It seems your pwd and location of bit file is same in this case. So how did you face this error ?

Regards,
Ashish
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Explorer
Explorer
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Registered: ‎09-14-2018

Hi Ashish,

In the command I posted I did not show the path at all just to simplify the view of it. It turned out this matters. I just copy and pasted the windows path and forgot to change the slash type. This cased weird errors.

By the way, what size should be use in the command -size 32 or 64? KCU105 has two FLASH memories, 32kB each.

Thank you.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-14-2014

Hello @arotenst ,

I just copy and pasted the windows path and forgot to change the slash type. This cased weird errors.

--> Can you please type this command with windows path which had shown error related to daisy chain? Because when I tried to use windows style path, I didn't get such weird error. So I want to reproduce this.

By the way, what size should be use in the command -size 32 or 64?

--> Size should be 64 because in this field, we specify total SPI flash memory size. The board has two 256 Mbit density flashe so total size is 512 Mbits which corresponds to 64 Mbytes (which we have to specify as value for -size field)

Regards,
Ashish
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Explorer
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Registered: ‎09-14-2018

HelIo Ashish,

Actually, I tried both 32 and 64 and it turns out both work. The problem I faced were two lines inn the constraint file:

set_property HD.TANDEM_IP_PBLOCK Stage1_Config_IO [get_cells sys_reset_n_ibuf]

set_property HD.TANDEM_IP_PBLOCK Stage1_Main [get_cells refclk_ibuf]

They were supposed to use to support Tandem PROM, but it turned out they caused halting configuration from FLASH, Why?

Also the biggest problem is (I can live without Tandem PROM for now) the PCIe core in my project is not visible by lspci. I used rdf0313 project as a base, assuming that it is the project, used for FPGA image, shipped with KCU105. It appears to be a different project. I cannot re-compile the project in Vivado 2018.3. The BIT file from the folder "ready_for_download" (I assumed, related to this project) behaves differently than the original image (no self diagnostic run).

The I think the PCIe/DMA core issue need to be addressed on different post.

Thank you.

 

 

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