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mckinjo4
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Registered: ‎05-22-2008

KTG K800 cannot program Spansion FL512S QSPI

I am using a hi-tech global k800 kintex ultrascale board and I am unable to program the flash using the Vivado Hardware manager. I am starting with a vendor created bin file. The configuration is Master SPI x4 mode. The schematic of the board matches the specified connections in ug570 for x4

I add the part in the hardware manager "s25fl512-s_x1_x2_x4", select the Bin file and hit program.

Blank check succeeds.

Erase fails.

Program fails with ""cannot set write enable bit or block(s) protected."

It also notable that the MFG ID, Memory Type, and memory capacity as read from the flash are reported correctly.

I have a feeling that there is something with the width of the spi interface, as AFAICT there is no WE bit in x4 mode.

 

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hj
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Registered: ‎06-05-2013

@mckinj04

Can you use the script attached to the AR https://www.xilinx.com/support/answers/61067.html
And read the xspi_read_statregs registers. Generally WP is volatile but if the configuration register (CR[3] ) is set to 1 then it becomes non-volatile & you might see above error message. Refer to page#48-49 https://www.cypress.com/file/177971/download

PS: Vivado doesn't touch this bit while programming or erasing.

Thanks
Harshit
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mckinjo4
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Registered: ‎05-22-2008

I had tried to use that script before my original post, but I guess I wasn't closely enough reading the directions, because I wnt back this morning and tried it again, and these area my results:

xspi_set_spi_clk
xspi_read_id
0 = A956
1 = A956
2 = 0050
3 = FF01
4 = 0220
5 = 4D00
6 = 8030
7 = 3182
8 = 0000
9 = 0000
10 = 0000
11 = 0000
12 = 0000
13 = 0000
14 = 0000
15 = 000E
Manufacturer ID : 01
Device ID
- memory type : 02
- memory capacity: 20
xspi_read_statregs
Status Register 1:
- bits [7:0] : 9E
Status Register 2:
- bits [7:0] : 00
Configuration Register :
- bits [7:0] : EA
xspi_prog_quad_enable 1
000e0000000000000000000000000000000000000000020001020018a956a956
Error: Possible prog error; max prog polling iteration reached

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mckinjo4
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Registered: ‎05-22-2008

So, EA =>> EA => CR[3] = 1, which means that BR[2-0] are volatile, and default on power on to 1, which is what SR1 shows their values to be.

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hj
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Registered: ‎06-05-2013

Registers seems to be correct. Do you see any issues with the power rails? Have you checked with Hitech global if they have any interface test which can be used here?

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