Kintex 7 CFGBVS effect on Vih and Vil of configuration pins

[mstember]

The CFGBVS on my Kintex 7 FPGA is tied to VCCO of 3.3V.  

After reading many documents it isn't clear what the threshold voltages are for the Vih and Vil.

In particular, what is the Vih and Vil for the CCLK?

Is there any hysteresis on CCLK?

[austin · Accepted solution]

m,

The dedicated IO are typically 8 to 12 mA LVCMOS.  There is no hysterysis.

The write_IBIS TCL command writes the IBIS models for your design.

LVCMOS Vil and Vih are typically between 1/3 and 2/3 of Vcco.

Proper signal integrity engineering is required for all pins, including and escpecially the dedicated ones used for configuration.  Most common mistake is to have a poor impedance match that causes reflections leading to clock glitches.

[mstember]

Hi Austin,

Thanks for the incredibly fast response with the data I need.

Mike

[pratham]

@mstember Glad to know you have got the information you are looking for. Information is availiable in UG470 #21

http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf