UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor canberkt
Visitor
474 Views
Registered: ‎09-15-2018

Kintex-7 ReConfiguration Problem

We use Kintex-7 FPGA on our own designed card. Although not on other cards, we are having a problem with FPGA on this card. Our problem: We cannot load the second configuration to Kintex.More specifically, after giving the card the first power, we can configure it. However, while this configuration is installed on the card, we cannot load the second configuration to Kintex.We can perform the loading process when we turn the power off and on again.
We need help with this problem.

My observations:
When I checked the pins in Jtag with the help of the oscilloscope, I observed that the "PROGRAM_B" signal was low. When I throw the first code, the "PROGRAM_B" bit is getting "high"and I can load the code. However, this does not happen in the second installation. Besides, Vivado can recognize FPGA over JTAG on the second configuration.

In the meantime, there was no such error on this card. I tried to use "Picoblaze JTAG Loader" on this card, and I suspect the error occurred after the "picoblaze" attempt.

Thank you for your comments.
Canberk.

0 Kudos
3 Replies
Moderator
Moderator
314 Views
Registered: ‎06-05-2013

Re: Kintex-7 ReConfiguration Problem

Hi Canberk,

Which config mode you are trying to use? Just JTAG?
Which version of tools you are using? Can you try to use 2018.2 or 2018.3 (Vivado lab tools) ?
Can you share the design properties using the below commands for the first design?
report_property -all [current_design] # make sure to open the implemented design
What happens if you just do a refresh_hw_device using Vivado HW manager GUI?

Thanks
Harshit
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Visitor canberkt
Visitor
266 Views
Registered: ‎09-15-2018

Re: Kintex-7 ReConfiguration Problem

Firstly, thanks for your response.
"2018.3", "2016.4", "2016.1" versions were used for these experiments. However, none of them showed a different situation.
Let me tell you from the beginning: the problem is solved as follows. However, it is not known exactly what caused or what was resolved.

I added "VIO" into the code. In this way, I was able to observe the operating status of the "VIO" after configuration. "VIO" worked properly. I have seen that the "input" and "output" ports of "VIO" could change.
After this process, surprisingly, "ReConfiguration Error" has been fixed.We could not understand what caused this situation. Was there some kind of a bug? And when "VIO" was added, the bug was fixed?

Thank you for your comments.
Canberk.

0 Kudos
Xilinx Employee
Xilinx Employee
229 Views
Registered: ‎08-10-2008

Re: Kintex-7 ReConfiguration Problem

This has no relationship with VIO. It should be that after you add VIO, bitstream is re-generated with different settings.

1. Did you set any special settings, such as encryption, readback forbidding in the previous 'first' configuration? Security settings can show these phenomeon.

2. Did the first configuration run as expected? If not,  this first configuration built some improper connection on board, resulting in key Config pins, such as INIT_B, at wrong voltage level, and lead to mess in Config circuit. Though I think the possibility is very low.

------------------------------------------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------------------