03-07-2020 03:47 AM
Hi Xilinx Team,
We are using Xilinx Kintex 7 XC7K325TFFG900 device in our project. Cypress S25FL128SAGMFI00 is used as the SPI Flash device. When we are using a 33 MHz CCLK, flashing through SPI is happening successfully. But when we use a 66MHz clock as CCLK, flashing is not happening. Please help to solve this issue.
Thanks & Regards,
03-07-2020 03:53 AM
03-08-2020 02:27 PM
The FPGA setup time for a Kintex-7 XC7K325T FPGA is 3.0 ns (for the current value, refer to DS182, Kintex-7 FPGAs Data Sheet).
The trace propagation delays from the CCLK to C pin and the longest propagation delay of any of the data pins provide TTPD. For this example, a rule of thumb of 165 ps per inch and a trace length of 6 inches from the FPGA to the SPI flash is used. (For more accurate results, other techniques such as IBIS simulation are recommended.)
A trace value of 12 inches at 165 ps/inch gives 2.0 ns.
1 / (7 ns + 3.0 ns + 2.0 ns) yields a clock frequency of 83.3 MHz. T
he designer should consider using the FPGA's internal oscillator and the closest value to 83.3 MHz is 66 MHz. However, the frequency tolerance (fMCCKTOL) for the XC7K325T is ±50% (for the current value, refer to DS182, Kintex-7 FPGAs Data Sheet) so this clock frequency could potentially be (66 MHz x 1.5) = 99 MHz, which would be too fast for the calculated maximum.
The next fastest configuration rate is 50 MHz, which has a maximum frequency of (50 MHz x 1.5) = 75 MHz. This rate is well below the calculated maximum and nominally operates at 50 MHz, which is well below the desired 83.3 MHz.
The bitstream of a Kintex-7 XC7K325T FPGA is 91,548,896 bits. 91,548,896 / 50,000,000 = 1.83 seconds to configure XC7K325T in x1 data width @ 50 MHz.
Try at 50Mhz see if that works for you.
03-08-2020 10:06 PM
The earlier cards in same batch were working perfectly at 66MHz clock frequency with the same trace length and propagation delay. The issue is seen in only this card. Since design wise there is no change, what will be the issue..?
03-09-2020 12:52 AM