UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor icogginsoda
Visitor
4,032 Views
Registered: ‎02-02-2017

Kintex Ultrascale XCKU060 + Tandem PROM + Bank 65 IO

I have a design using a '060 Kintex Ultrascale, with the PCIE DMA core. I need to meet the PCIE spec for 100ms boot so had provisioned for Tandem PROM boot mode.

 

I finally got far enough in the implementation step and am told that all my IO in bank 65 is conflicting with stage 1 and stage 2 IO. In particular it says I cannot put user IO in bank 65 ?

 

I cannot find anything in the PG/UG that talks about this. I'm not using dual purpose config pins- these are general IO. Why can I not use bank 65 ??

 

I also have a related problem in that I'm using the dedicated PERSTN pin that happens to be in pin 65. And so is included in the tandem stage 1 pblock.  It seems that is also causing problems with stage 2 IO being in bank65 as it thinks it is in the same pblock. Can I just modify this tandem pblock to exclude the other IO Pins? OR are they all lumped together ?

 

I am using almost every IO on the device. I have to use bank65 for IO... but how can I get Tandem boot modes to work ? Will Tandem PCIE work around the issue? How about the pblock error?

 

 A couple of examples from the impl. results below.

“[DRC 23-20] Rule violation (HDTC-6) Non-stage-one logic illegally placed - Non-stage-one logic 'AUR_CLK_SEL_OBUF_inst' is placed at site 'IOB_X2Y94' inside stage one Pblock 'pcie_ep_tandem_i_inst_pcie3_ip_i_inst_Stage1_cfgiob'.  Non-stage-one logic should not be placed inside a stage one region.

 

 

[DRC 23-20] Rule violation (HDTC-6) Non-stage-one logic illegally placed - Non-stage-one logic 'cam_subsystem_top_i/cam0_chan_top/xxxxxx_axi4l_fabric_inst/IOBUF_cam_spi_miso_i/OBUFT (in cam_subsystem_top_i/cam0_chan_top/xxxxxx_axi4l_fabric_inst/IOBUF_cam_spi_miso_i macro)' is placed at site 'IOB_X2Y57' inside stage one Pblock 'pcie_ep_tandem_i_inst_pcie3_ip_i_inst_Stage1_cfgiob'.  Non-stage-one logic should not be placed inside a stage one region.

 

...

 

[DRC 23-20] Rule violation (HDTC-10) Config banks not available to second stage I/O - For Tandem PROM flow, second stage I/O 'xxxxxx_inst' can not use configuration bank '65'.

 

 

0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
3,792 Views
Registered: ‎11-17-2008

Re: Kintex Ultrascale XCKU060 + Tandem PROM + Bank 65 IO

The granularity of configuration in Xilinx devices is the height of a clock region, which matches the size of an IO bank.  In order to bring the PCIe reset pin (which by default is in Bank 65), then entire bank must be configure.  This means any user IO that must also go in this bank would come up with stage 1.  To make sure that you're clear that this will happen so you understand the potential behavior of IO with no logic yet driving it, we ask that you explicitly add these IO (and any other elements that fall into this configuration frame) to the stage 1 pblock.

 

Details, including constraint syntax, on how to do this is given in PG156, pages 105-107.

https://www.xilinx.com/support/documentation/ip_documentation/pcie3_ultrascale/v4_2/pg156-ultrascale-pcie-gen3.pdf

 

In general, we suggest that users avoid Bank 65 whenever possible, not only to avoid conflicts with Tandem Configuration, but to simply avoid the use of these special dual-purpose pins.  But if that is unavoidable (such as your case), the identification of resources needed for stage 1 will get you past these errors.

 

thanks,

david.

0 Kudos