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Registered: ‎01-14-2019

Kintex Ultrascale+: error on Jtag Programming - [Labtools 27-3165] End of startup status: LOW

Dear Support,

we have designed a board with 2 xcku9p FPGAs connected in chain.

We have succesfully programmed them using Slave Serial Mode, but we are failing the programming phase via Jtag with the following error:

ERROR: [Labtools 27-3165] End of startup status: LOW

( Vivado Lab version 2019.1 on Windows 7 and 10, Platform Cable USB II)

We have searched the forum and found a similar issue where was suggested to check the cable speed, but nothing changed (Speed 750000 up to 6000000)

In attach you can find the register dump excel.

We provide also the piece of schematic related to the FPGA programming pins (please notice that wrt the schematic we already changed some resistor values to align to a Xilinx demo board). VCC_AUX and MAN_1V8 are 1V8 .

Could you suggest us how to solve the issue?

thanks!

Regards,

Giovanna

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Moderator
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Registered: ‎06-05-2013

Re: Kintex Ultrascale+: error on Jtag Programming - [Labtools 27-3165] End of startup status: LOW

Can you provide the following details.

Do you see both the devices in the JTAG chain correctly?
Can you try to assign the bitstream individually to these devices & capture the status registers. From the above shared status registers its hard to locate the root cause.

>Also open the implemented design and run the below command:-
>report_property -all [current_design]

Harshit
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Registered: ‎01-14-2019

Re: Kintex Ultrascale+: error on Jtag Programming - [Labtools 27-3165] End of startup status: LOW

Hi Harshit,

thanks for replying.

1) Yes, we see the JTAG chain correctly.

2) In attach two spreadsheets one related to FPGA_0 and the other to FPGA_1. Since the programming never succeded they are related to unprogrammed devices obviously.

3)report_property - all [current_design]

 

Property                                    Type     Read-only  Value
BITSTREAM.AUTHENTICATION.AUTHENTICATE       enum     false      
BITSTREAM.AUTHENTICATION.RSAPRIVATEKEYFILE  file     false      
BITSTREAM.CONFIG.BPI_1ST_READ_CYCLE         enum     false      
BITSTREAM.CONFIG.BPI_PAGE_SIZE              enum     false      
BITSTREAM.CONFIG.BPI_SYNC_MODE              enum     false      
BITSTREAM.CONFIG.CCLKPIN                    enum     false      
BITSTREAM.CONFIG.CONFIGFALLBACK             enum     false      
BITSTREAM.CONFIG.CONFIGRATE                 enum     false      
BITSTREAM.CONFIG.D00_MOSI                   enum     false      
BITSTREAM.CONFIG.D01_DIN                    enum     false      
BITSTREAM.CONFIG.D02                        enum     false      
BITSTREAM.CONFIG.D03                        enum     false      
BITSTREAM.CONFIG.DCIUPDATEMODE              enum     false      
BITSTREAM.CONFIG.DONEPIN                    enum     false      
BITSTREAM.CONFIG.EXTMASTERCCLK_EN           enum     false      
BITSTREAM.CONFIG.INITPIN                    enum     false      
BITSTREAM.CONFIG.INITSIGNALSERROR           enum     false      
BITSTREAM.CONFIG.M0PIN                      enum     false      
BITSTREAM.CONFIG.M1PIN                      enum     false      
BITSTREAM.CONFIG.M2PIN                      enum     false      
BITSTREAM.CONFIG.NEXT_CONFIG_ADDR           hex      false      
BITSTREAM.CONFIG.NEXT_CONFIG_REBOOT         enum     false      
BITSTREAM.CONFIG.OVERTEMPSHUTDOWN           enum     false      
BITSTREAM.CONFIG.PERSIST                    enum     false      
BITSTREAM.CONFIG.PROGPIN                    enum     false      
BITSTREAM.CONFIG.PUDC_B                     enum     false      
BITSTREAM.CONFIG.RDWR_B_FCS_B               enum     false      
BITSTREAM.CONFIG.REVISIONSELECT             enum     false      
BITSTREAM.CONFIG.REVISIONSELECT_TRISTATE    enum     false 

 

Thanks

bye

Giovanna

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Registered: ‎01-14-2019

Re: Kintex Ultrascale+: error on Jtag Programming - [Labtools 27-3165] End of startup status: LOW

Hi Harshit,

any news on our problem?

 

thanks

Giovanna

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Registered: ‎06-05-2013

Re: Kintex Ultrascale+: error on Jtag Programming - [Labtools 27-3165] End of startup status: LOW

Hi Giovanna,

Somehow above properties doesn't have any data. Are you setting any design properties in TCL file before generating the bitstream
If so please share the properties before the write_bitstream command.

Assign .bit to both the devices in chain and try to program the device. It seems to be case where Done for both the devices are connected together and one(unconfigured device) is driving it low.

Is there a way to separate (HW jumper) done and init_b for both the devices during JTAG programming so that each device can configure separately?

Thanks
Harshit
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Re: Kintex Ultrascale+: error on Jtag Programming - [Labtools 27-3165] End of startup status: LOW

Hi Harshit,

we do not set properties in tcl.

Regarding the done signals, no they are not connected together, they are separated.

Also init_b are separated.

Therefore we can try to program only one of the two FPGA, but unluckily the programming does not succeed.

Bye

Giovanna

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Re: Kintex Ultrascale+: error on Jtag Programming - [Labtools 27-3165] End of startup status: LOW

Hello,

 

any comments on our problem?

we still do not know why JTAG programming is not working ....

 

thanks

Giovanna

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Xilinx Employee
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Registered: ‎01-21-2013

Re: Kintex Ultrascale+: error on Jtag Programming - [Labtools 27-3165] End of startup status: LOW

Hi @giovanna.ferrara ,

 

I’d be interested in seeing your bitstream settings.

The properties you previously sent seem to have no data.

Would it be possible to provide all of the bitstream settings you have used in your XDC file?

I would be interested in seeing the order of events in the startup sequence such as GTS and DONE.

 

Also the Table0.xlsx and Table1.xlsx didn’t provide the status register output of the failed programming, like the output captured in Registers.xlsx.

Would you be able to capture the status registers for the test that was previously asked:

“Can you try to assign the bitstream individually to these devices & capture the status registers.”

 

Thanks in advance.

Thanks,
Wendy
Xilinx Technical Support
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Re: Kintex Ultrascale+: error on Jtag Programming - [Labtools 27-3165] End of startup status: LOW

Hello,

sorry for incorrect and empty tables.xls: I attached by mistake.

The correct ones are in attach now (Table0.xls for xcku9p_0,Table1.xls for xcku9p_1).

I tried to program the fpga0, the operation failed, I exported the properties in excel table0.xls; then I did the same steps on fpga1

Regarding the bitstream properties, we generated the bitstream with standard Vivado 2019.1 settings and we do not set any special value by xdc/tcl.

 

Thanks a lot for support

Bye

Giovanna

 

 

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Registered: ‎01-14-2019

Re: Kintex Ultrascale+: error on Jtag Programming - [Labtools 27-3165] End of startup status: LOW

Hi!

any feedback on the infi I provided ?

We still have the problem....

Thanks

Giovanna

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Registered: ‎01-14-2019

Re: Kintex Ultrascale+: error on Jtag Programming - [Labtools 27-3165] End of startup status: LOW

Hello,

we have not  still not found a root cause of this problem. Can someone help? thanks a lot

Giovanna

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