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Adventurer
Adventurer
10,357 Views
Registered: ‎05-29-2014

LVDS25 not correct voltage levels initialization of the device

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I'm facing a very strange behaviour of the XC7K325 in my board. I have many LVDS25 outputs. These outputs are directly connected to other components (not FPGAs) whose inputs have an embedded 100 ohm termination resistor.

The strange behaviour is present in a certain number of outputs, and not in all the boards.

After the power-on phase, when the FPGA is not configured, the voltage at the positive output is about 1.8V.

Then the board controller configures the other FPGAs in the board and the voltage level goes to about 2.5V.

Then the XC7K325 is configured and the voltage level remains at 2.5V.

The FPGA, internally, is correctly configured and working, but the LVDS output remains at 2.5V.

I checked and I found that this the output is not in tristate.

The negative output of the same LVDS25 output has the same behaviour of the positive one.

Then I connect the JTAG cable and start the hardware manager of Vivado. Immediately after the connection the voltage of the output goes to a correct value (about 1V) and the output starts to work correctly.

It is a very strange behaviour and I don't know how to solve it. And why when I connect to the board with the JTAG cable, the correct voltage value is restored??

Regards

Davide

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Scholar pratham
Scholar
20,233 Views
Registered: ‎06-05-2013

Re: LVDS25 not correct voltage levels initialization of the device

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@davide.camerano I am sure it would fix the problem.

 

The DONE signal is released before EOS. Thus, the processor code must not stop delivering the bitstream or stop delivering CCLK pulses when DONE transitions to High. 

 

A few BitGen options affect FPGA start-up by potentially extending the start-up sequence beyond the end of the delivered bitstream. For a few of these options, additional CCLK pulses must be issued to the FPGA after the delivery of a configuration bitstream. Example BitGen options that affect start-up include LCK_CYCLE or MATCH_CYCLE.

To cover all possible bitstream start-up options, the processor code must be written to:

1. Load all the bitstream data.

2. Continue to apply CCLK cycles (while the data bits on D01_DIN or D[31:00] are all ones) until DONE is asserted High.

3. Apply eight additional CCLK cycles after DONE is asserted High to ensure completion of the FPGA start-up sequence.

-Pratham

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4 Replies
Adventurer
Adventurer
10,337 Views
Registered: ‎05-29-2014

Re: LVDS25 not correct voltage levels initialization of the device

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I found that, during the configuration of the Xc7K325, after the DONE signal has gone high, sending 8 additional clocks to the CCLK pin some of the outputs goes to the correct level. But not all. Is there any rule, or any document explainig exactly how many clocks (or wait time or other) are needed?

regards

Davide

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Scholar pratham
Scholar
10,335 Views
Registered: ‎06-05-2013

Re: LVDS25 not correct voltage levels initialization of the device

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@davide.camerano Are you using slave serial interface?

If yes, best practice (to cover all possible bitstream start-up options) is to load all the data from the configuration file,​ continue to apply CCLK cycles until DONE is asserted High,​ and finally,​ apply eight additional CCLK cycles after DONE is asserted High to ensure completion of the FPGA start-up sequence.

-Pratham

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Give Kudos to a post which you think is helpful and reply oriented.
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Adventurer
Adventurer
10,331 Views
Registered: ‎05-29-2014

Re: LVDS25 not correct voltage levels initialization of the device

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Yes, I'm using the Slave serial protocol. What you suggested is exactly what I do. Now it works, and we are completing our tests to verify if the problem is present or not.

regards

Davide

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Scholar pratham
Scholar
20,234 Views
Registered: ‎06-05-2013

Re: LVDS25 not correct voltage levels initialization of the device

Jump to solution

@davide.camerano I am sure it would fix the problem.

 

The DONE signal is released before EOS. Thus, the processor code must not stop delivering the bitstream or stop delivering CCLK pulses when DONE transitions to High. 

 

A few BitGen options affect FPGA start-up by potentially extending the start-up sequence beyond the end of the delivered bitstream. For a few of these options, additional CCLK pulses must be issued to the FPGA after the delivery of a configuration bitstream. Example BitGen options that affect start-up include LCK_CYCLE or MATCH_CYCLE.

To cover all possible bitstream start-up options, the processor code must be written to:

1. Load all the bitstream data.

2. Continue to apply CCLK cycles (while the data bits on D01_DIN or D[31:00] are all ones) until DONE is asserted High.

3. Apply eight additional CCLK cycles after DONE is asserted High to ensure completion of the FPGA start-up sequence.

-Pratham

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post