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17,005 Views
Registered: ‎03-31-2016

[Labtools 27-3165] End of startup status: LOW

I get the following error when i try to program the Artix-7 FPGA through the JTAG port using Platform Cable USB II on my board.  I try the same thing on a different board and it works without any issues.  What could be causing this error?  I have looked at all signals and voltages around the FPGA and all are identical between the two boards.  

 

I looked at another post with similar error message and it did not help.  I NEED HELP.......

 

set_property PROBES.FILE {} [lindex [get_hw_devices] 0]
set_property PROGRAM.FILE {C:/_Projects-FPGA/FTU100a2/FTU100a2.runs/impl_2/FTU100a2.bit} [lindex [get_hw_devices] 0]
program_hw_devices [lindex [get_hw_devices] 0]
ERROR: [Labtools 27-3165] End of startup status: LOW
program_hw_devices: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1713.832 ; gain = 0.000
ERROR: [Common 17-39] 'program_hw_devices' failed due to earlier errors.

20 Replies
Xilinx Employee
Xilinx Employee
16,995 Views
Registered: ‎04-16-2012

Re: [Labtools 27-3165] End of startup status: LOW

Hi jn.shah55@gmail.com

 

Did you try reducing the cable speed?

Are you using the same bit file for programming in other boards?

 

Thanks,

Vinay

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16,992 Views
Registered: ‎03-31-2016

Re: [Labtools 27-3165] End of startup status: LOW

Hello Vinay, yes & yes.  What else should i look for?

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16,987 Views
Registered: ‎03-31-2016

Re: [Labtools 27-3165] End of startup status: LOW

Hello Vinay, wrong answer from me.  How do i reduce the cable speed from the Hardware Manager in Vivado 2016.1?  If i remember it correctly, that option was available in Impact, but i don't see that in Hardware Manager.

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Xilinx Employee
Xilinx Employee
16,982 Views
Registered: ‎04-16-2012

Re: [Labtools 27-3165] End of startup status: LOW

Hi jn.shah55@gmail.com

 

Follow below steps to reduce the cable speed:

 

1. Open HW Manager in Vivado GUI

2. Click on Open Target and select Open New Target

3. Click Next twice

4. In the "Hardware Targets" window, you will find the JTAG Clock Frequency.

5. Click on the drop-down and select the frequency.

 

Thanks,

Vinay

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16,981 Views
Registered: ‎03-31-2016

Re: [Labtools 27-3165] End of startup status: LOW

Hello Vinay, it works without any issues with exactly the same setup and same .BIT file, if i change out my current board with an exactly similar board.  Only difference is that on the good board I get the "INFO: [Labtools 27-3164] End of startup status: HIGH" message instead of "ERROR: [Labtools 27-3165] End of startup status: LOW" message......

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16,980 Views
Registered: ‎03-31-2016

Re: [Labtools 27-3165] End of startup status: LOW

Tried out all clock speed options.  No change.  Still get the same error on End of Startup Status: LOW

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16,956 Views
Registered: ‎03-31-2016

Re: [Labtools 27-3165] End of startup status: LOW

Hi Vinay, any suggestions?

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Xilinx Employee
Xilinx Employee
16,954 Views
Registered: ‎04-16-2012

Re: [Labtools 27-3165] End of startup status: LOW

Hi jn.shah55@gmail.com

 

Share the status registers after programming failure.

 

Thanks,

Vinay

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16,922 Views
Registered: ‎03-31-2016

Re: [Labtools 27-3165] End of startup status: LOW

Hi Vinay, can you please tell me the steps to read back the status register after the failure?

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13,904 Views
Registered: ‎03-31-2016

Re: [Labtools 27-3165] End of startup status: LOW

Hi Vinay, see attached file for all the status registers info after the most recent programming failure.  Please let me know if you see anything that I am missing.

 

Thanks,

Jay Shah

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13,893 Views
Registered: ‎03-31-2016

Re: [Labtools 27-3165] End of startup status: LOW

Hi Vinay, did you get a chance to look at the status register details?  

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Xilinx Employee
Xilinx Employee
13,885 Views
Registered: ‎02-14-2014

Re: [Labtools 27-3165] End of startup status: LOW

Hello jn.shah55@gmail.com,

 

Few other pointers to narrow down the issue further -

 

1. Do you observe this issue even if you try to configure this device with any other bitstream ?

2. Can you check if your design has any critical warnings / warnings related to this error ?

3. Is it possible to assign PACKAGE_PIN and IOSTANDARD constraints to each IO port and check if it solves the issue ?

Regards,
Ashish
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13,863 Views
Registered: ‎03-31-2016

Re: [Labtools 27-3165] End of startup status: LOW

Hello Ashish, answers to your questions:

(1) same result when used with other .BIT file

(2) I need to check warnings.  I will report in next message

(3) I do have PACKAGE_PIN and IOSTANDARD assigned to each IO port.  See attached XDC

 

Thanks,

Jay Shah

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Explorer
Explorer
13,425 Views
Registered: ‎08-04-2016

Re: [Labtools 27-3165] End of startup status: LOW

Hello jn.shah55@gmail.com

 

Were you able to find a solution to the problem?

I get the same problem in Ubuntu 14.04, whereas the cable is not even detected in Windows 10.

Please let me know if you find the solution,

 

Regards,

Rajat Rao

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13,404 Views
Registered: ‎03-31-2016

Re: [Labtools 27-3165] End of startup status: LOW

Hello Rajat, my problem was the signal integrity on JTAG interface connections to the FPGA (Artix-7).  Specifically, the clock (TCK) signal.  See attached JPG images for the proper JTAG termination.  Once I did this, I do not have a problem anymore.  Since my board is already laid out and fabricated, I did not implement the buffering also recommended for the JTAG interface.

 

I also had improper termination on the 4-bit data bus between the flash PROM and the FPGA.  I am using the flash in SPIx4 mode.  I corrected the interface by changing the series resistors to 100 ohms on the data bus.

 

Hope this helps.

 

Jay Shah

JTAG Termination Buffers.JPG
JTAG Termination.JPG
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Voyager
Voyager
7,441 Views
Registered: ‎10-12-2016

Re: [Labtools 27-3165] End of startup status: LOW

Hi jn.shah55@gmail.com@rajatrao @ashishd @vuppala

 

I am getting same issue, can you please let me know the exact reason ?

 

I am using xc7k410tffg676-2c part for customboard and JTAG_SMT2 for FPGA programming interface. FPGA part detected but not programmed . 

 

Any help or suggestions are highly appreciated. 

 

Thank you 

S Sampath 

-Sampath
Newbie nikithsai
Newbie
6,610 Views
Registered: ‎07-12-2018

Re: [Labtools 27-3165] End of startup status: LOW

Hello jn.shah55@gmail.com

 

I also got the same error. But I had solved it by reconnecting the whole device by rebooting my PC and re-powering the ZED Board.

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3,027 Views
Registered: ‎02-04-2019

Re: [Labtools 27-3165] End of startup status: LOW

I am using Vivado 2018.3, trying to programme an Artix XC7A50T on a custom board via an interface board using the HW Manager and the Platform Cable USB II  . I can see the chain (comprising of the FPGA and an PIC). When I attempt to programme the FPGA only, with my .bit file I get the

ERROR: [Labtools 27-3165] End of startup status: LOW

error. I have tried lowering the jtag clock speed.  We are in the process of trying to isolate where the issue lies. Could you please advise what kind of Vivado warnings (generated during synthisis and implementation) could give rise to this error. Thanks.

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Visitor clarelai
Visitor
2,645 Views
Registered: ‎10-25-2018

Re: [Labtools 27-3165] End of startup status: LOW

I found a solution........

ERROR: [Labtools 27-3165] End of startup status: LOW" after FPGA programming
Insufficient external power supply can cause this issue. If power supply is insufficient, module restarts and FPGA content is erased. Vivado did not recognize this.

Link: https://wiki.trenz-electronic.de/display/PD/FAQ
989 Views
Registered: ‎04-06-2017

Re: [Labtools 27-3165] End of startup status: LOW

I have faced this issue multiple time in Artix 7 SOM. The only way to make the issue go is:

a. The design should have an external explicit reset,

b. Debug any issue if available in the reset circuit.

c. make sure configuration pins are all pulled up/ pulled down correctly

d. reset is not floating

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