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Contributor
Contributor
362 Views
Registered: ‎05-11-2018

MMCM ith no activity on input signal

Hi,

    I' m wondering what is happening to the output clock of an MMCM/PLL in case the input is fixed. I've tried to view it with a post implementation timing simulation and I see that is fixed to '0'. Is this happening also in hardware or instead the output clocks are moving?

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Xilinx Employee
Xilinx Employee
348 Views
Registered: ‎06-13-2018

Hi fcaldi@92 :

Which signals are you monitoring? is the LOCKED signal asserted?

What is the input clock frequency? What is the clock source? Can you share .xci file here? Also, please share the simulation screenshot.

 

 

Thanks,

Priyanka

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Contributor
Contributor
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Registered: ‎05-11-2018

Hi @panantra,

                       you can simply replicate what I did because I only generated the IP example design using vivado 2017.1 (but I think that for every version is the same) and the default values for the IP. The simulation is screenshot is the following

screenshot.png

Looking at simulation the clock is at rest. My question is if also the hardware is behaving in the same way because I'm supposing that if the PLL is not resetted or in power down the VCO will have a minimum frequency. So in that case I suppose is happening the following:

-lock signal never asserted

-output clock equal to minimum frequency of VCO multiplied by the ratio of coefficients of the MMCM/PLL loop and output clock dividers

Are my hypothesis correct?

 

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Xilinx Employee
Xilinx Employee
270 Views
Registered: ‎06-13-2018

Hi fcaldi@92 :

I generated a PLL example design in Vivado 2019.2, run post-implementation timing simulation. I see input and output clock as well as LOCKED is asserted.

You need to run the implementation from here once it is launched:

PLLexSimulation.JPG

My question is if also the hardware is behaving in the same way because I'm supposing that if the PLL is not resetted or in power down the VCO will have a minimum frequency. 

   --- No, you are observing simulation, it's not implemented on actual hardware yet. You can monitor the status of PLL on hardware as well using the Integrated Logic Analyzer. 

 

Thanks,

Priyanka

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Contributor
Contributor
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Registered: ‎05-11-2018

Hi @panantra,

                        I know that I need to implement and launch the simulation. My clock input id '0' because is forced by hand to '0'. I was only asking information about how the hardware behaves in reality. I expect the behaviour that i mentioned previously in the VCO but I don't know if PLL and MMCM have other signals acting on the generated clock in order to mute them. By the way I'll try monitoring it through hardware to retrieve the information

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