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shidaxingpan
Visitor
Visitor
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Registered: ‎10-23-2019

Manage the version of the fpga project by the tcl

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During FPGA development, We need to develop multiple versions of the FPGA project,and program them into the FPGA to debug..But the question is that  we can not  determine which version of the current FPGA is,except to program a new bit/mcs file into the FPGA.that is very inconvenient. We want to add a register into the verilog code.when we complile the FPGA project,the register update automatically. Besides,we want to add another register , it update automatically,when we modify the version number of the FPGA project. and the version number is the numeric suffix of the project folder name.Then,we can read back that register through the pie bus,to determine the current FPGA version.is anyone can help me? or proved some reference documents.Thanks,very much!

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wduffy
Xilinx Employee
Xilinx Employee
416 Views
Registered: ‎01-21-2013

Hi @shidaxingpan,

 

What FPGA are you using?

Have you considered using the USR_ACCESSE2 primitive or the BITSTREAM.CONFIG.USERID bitstream setting for managing design revisioning?

 

USR_ACCESSE2 is documented in UG570 for the UltraScale devices. 

https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf

 

BITSTREAM.CONFIG.USERID is documented in UG908 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug908-vivado-programming-debugging.pdf

 

Thanks,
Wendy
Xilinx Technical Support
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wduffy
Xilinx Employee
Xilinx Employee
417 Views
Registered: ‎01-21-2013

Hi @shidaxingpan,

 

What FPGA are you using?

Have you considered using the USR_ACCESSE2 primitive or the BITSTREAM.CONFIG.USERID bitstream setting for managing design revisioning?

 

USR_ACCESSE2 is documented in UG570 for the UltraScale devices. 

https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf

 

BITSTREAM.CONFIG.USERID is documented in UG908 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug908-vivado-programming-debugging.pdf

 

Thanks,
Wendy
Xilinx Technical Support
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shidaxingpan
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Registered: ‎10-23-2019

Thank you very much!Now we use the "USER_ACCESS"primitive in Virtex-7 FPGA.And we can get the time of the bit stream generation.

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