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Observer
Observer
10,613 Views
Registered: ‎01-10-2013

Master SPI Config : Different voltage level

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I'm currently designing a system using an Artix XC7A200T-1156 and I'm forced to relocate DDR3 on banks 13,14 and 15. Because of this I have to drop the VCCO banks to 1.5V which are incompatible with the voltage levels described on XAPP586 (either 1.8V or 2.5/3.3V) for master SPI configuration.

 

Is it possible to use voltage translators to interface the SPI flash (as described in XAPP520) ? Would it cause problems if VCCO_14 is different from the voltage set by the CFGBVS pin? 

 

There are already some posts on this issue but all are inconclusive. I would really appreciate if some insight is be given on this problem (or if someone already tried the voltage translator solution).

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Xilinx Employee
Xilinx Employee
18,295 Views
Registered: ‎10-11-2007

1) Banks 0 and 14 both at 1.5V will work just fine (CFGVBS = 0).

 

3) If you use only JTAG to configure the part (MCU or otherwise) then only bank0 is required for configuration.  The Vcco bank voltage for 14+15 can be any.

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Xilinx Employee
Xilinx Employee
10,509 Views
Registered: ‎01-03-2008

> Would it cause problems if VCCO_14 is different from the voltage set by the CFGBVS pin?

 

Yes, this will be a problem.  If you are using configuration pins in banks 14 & 15 they need to be using the same VCCO as bank 0.

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Xilinx Employee
Xilinx Employee
18,296 Views
Registered: ‎10-11-2007

1) Banks 0 and 14 both at 1.5V will work just fine (CFGVBS = 0).

 

3) If you use only JTAG to configure the part (MCU or otherwise) then only bank0 is required for configuration.  The Vcco bank voltage for 14+15 can be any.

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Observer
Observer
10,484 Views
Registered: ‎01-10-2013

Thanks for your prompt help :)

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