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Visitor
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Registered: ‎04-17-2015

Method to Program BBRAM and eFUSE KEY

Hi Everyone.

We are using Artix-7  XC7A12T.   We need to use an encrypted bitstream.

Whenever I try to program either BBRAM OR eFUSE KEY, I get this error:

ERROR: [Labtools 27-3105] HW Server Error: Fuse Key does not match

 

If I use a key of all 0's, it works fine, but of course, not a useful key.

If I set even one bit in the key, it fails - So I guess it is verifying the key, just not able to program it.

Note:  I can use an encrypted bitstream, if I use a key of all 0's, so I think everything is working except for the programming of the key.

VCCBat is 1.8V

I tried forcing config mode to JTAG(An errata for a different device) - No change.

Setting clock to 3MHz does not help.

I have seen posts related to UltraScale needing a third party tool, but nothing related to 7-series.  In fact I can't find any errata related to 7-series Fuses after Vivado release 17 or so...

Any advice is appreciated.


Thanks,

Tony

 

 

 

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Visitor
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Registered: ‎04-17-2015

Just adding some detail:

I am using Vivado 2018.3 64-Bit Hardware Manager and Platform Cable USB II in my attempts to program BBRAM and eFUSE.

 

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Registered: ‎04-17-2015

I am updating this again - Hoping to find somebody that has programmed the Encryption key on Artix-7 ... Maybe you are able to spot what I am doing wrong.

Yesterday I installed the latest version ov Vivado (2020.1 (64-bit), on Windows 10

I get the same result.    If I use a key of all 0's, it is fine (0's are the default values of the fuses)

If I set any bits in the key, it fails to program.

     Same result whether I try BBRAM or eFUSE.

     I attached two key files and result slides from my experiments.

Has anybody programmed Artix-7 using Vivado?

 

Thanks.

 

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Registered: ‎04-17-2015

I think this may be a Xilinx bug:  

When the FPGA is second in the chain, programming BBRAM or eFUSE Encryption Key fails, but if it is the only device on the JTAG chain, it works fine.

We have a suitable resolution, but I will leave this issue open - Maybe someone from Xilinx could check/verify whether they agree that the FPGA needs to be first in the JTAG chain.

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