06-09-2020 08:07 AM
Is it possible to boot a Microblaze application from an SD card via AXI Quad SPI? And how do I implement it?
I know that this can be done using SPI flash by creating an SREC bootloader application and burning the SREC file at a specific location in SPI Flash. But can this be done via an SD card?
I wish to be able to store the microblaze application on the SD card and load it into DDR memory. I couldn't find any information about this feature apart from those for Zynq FPGAs which uses a different system.
To clarify I DO NOT wish to program the FPGA via an SD card. I only want to load a Microblaze application.
I would appreciate any feedback on the above.
06-09-2020 09:49 AM
06-09-2020 11:31 AM
I think the "magic" is going to happen with the FSBL. if you load the BRAMs for the MicroBlaze processor with an FSBL that is configured to load from the SD card, then, the boot sequence can look like this...
From the hardware side you will need to:
1) create your hardware design with peripherals, caches, and whatever else you want. Make sure there is a DDR controller (which is covered in the next item...)
2) customize the MicroBlaze to use DDR. This will usually instantiate a DDR controller or use the DDR controller in the PS if you are using a Zynq device.
3) generate your bitstream as usual
From the software side:
1) Using the Vitis IDE, modify the FSBL so that it is set to only boot from the SD Card. This would be done by modifying the code in the platform project. (There are certain compiler SYMBOLS that can be selected to do this as well as removing unnecessary parts of the FSBL such as QSPI drivers. We have an educational module on debugging the FSBL which goes through much of this process. It's not too difficult and running through the example lab shows you how it is done. There will be some differences as the lab is geared towards the MPSoC devices, but the concepts are the same for the MicroBlaze).
2) Create an application project that you want to run from the DDR. This is just whatever it is that you need to run. The fact that it's running from DDR isn't that important - although you may want to visit the linker script to make sure that everything that you want is being placed in DDR. Check out our LinkerScript lesson as it discusses how to create your own sections and put them into the type of memory that you want. (There is both a lecture and lab on this). Typically, low-latency items such as scratch-pad data, interrupt handlers, etc. are kept in BRAM as it is available within a dozen clock cycles or so as opposed to DDR which can take up to a few hundred clock cycles to access. Remember that DDR is great for moving large volumes of data quickly, but stinks for pulling individual datum out.
3) Build a bootable image for the SD Card.
4) You can either load the FSBL into the MicroBlaze's BRAMs so that it runs the FSBL (which copies from the SD Card to DDR) as soon as the MicroBlaze is released from reset OR (easier) just leave the default boot code in the MicroBlaze's BRAMs and that will go out to the SD Card and load the FSBL into the BRAM, and run it. With the FSBL running, the code will be copied from the SD Card into DDR, then control will be transferred to it and you will have (hopefully) an operational MicroBlaze system.
Let me know if you want more details on anything...
06-10-2020 07:32 AM
Thanks for your reply.
Vitis IDE 2019.2 and Vivado SDK 2019.1 do not offer FSBL application projects for Microblaze base systems. Is there a particular version that support Microblaze FSBL or is there some way to get around this?
06-10-2020 01:39 PM
I'm building up an example design in 2020.1 to see if an FSBL is available for the uB. I'm targeting a "pure" FPGA device, that is, no PS. Hopefully, I'll have some kind of answer for you tomorrow.
06-15-2020 08:47 AM
I created a MicroBlaze only design (very simple as we are only looking to see what the Vitis IDE is providing as support).
So far, I've exported the design from Vivado and created a platform project in the Vitis IDE. Unlike the MPSoC platforms, it appears as though the FSBL is not automatically generated. This may be because the MicroBlaze's BRAMs can be pre-loaded with the FSBL or the application.
When I attempt to create a new application project, (as you pointed out previously), I am not seeing an FSBL application template.
There is, however, an mba_fs_boot template, as well as an SREC and SREC SPI Boot loader.
There is a (dated) tutorial on the Arty board for the SREC [SPI] Boot loader here: https://www.avnet.com/opasdata/d120001/medias/docus/178/UG-AES-A7MB-7A35T-G-Arty-SREC-Bootloader-VIV2015-2-V1.pdf
I'll reach out to the Xilinx internal team to see why the old FSBL template is missing.
Thanks for your patience!
06-15-2020 02:15 PM
OK, so here's what I learned...
MicroBlaze never supported the FSBL - the FSBL is a Zynq-7000/MPSoC/RFSoC/... kind of thing. That said, there is the FS-Boot which is a minimal bootloader that can be loaded into the BRAM and does enough to get an SSBL (like U-Boot) up and running. U-Boot can definitely load from the SD card.
I'm currently browsing for documentation, but the long and short of it is this: use FS-Boot to load U-Boot and set up U-boot to load from the SD card.
06-15-2020 02:22 PM
And the follow-up:
Usually, FS-Boot is used for booting Linux, but because it brings in the more capable U-Boot, you'll probably want to use it.
It's here on the public Xilinx GitHub:
It’s tiny - all it does is init the config interface & UART, init the DDR, load the U-Boot into DDR, then hands-off control to U-Boot.
I hope this gets it done for you!
06-23-2020 08:00 AM
09-18-2020 12:57 AM
Now I am doing the same scheme to realize spi startup with xcvu440(2017.4).Disable the STARTUP2E primitive. I did not create an application, but directly created the srec SPI boot loader application project. but now we report an error when writing QSPI:
ERROR: [Xicom 50-48] Start address (0x00000000) is outside of the device memory range.
Can you give me some advice?
10-02-2020 12:36 AM