02-05-2018 07:09 AM
we try to get in system BPI update of the Micron flash chip 28f256p33b-bpi-x16 (P33) via SVF file working. The flash holds the FPGA configuration of a connected Artix 200 (xc7a200tffg1156-2).
We generate the SVF file from the BIN file via Vivado 2017.4. The file is run by the LIB(X)SVF JTAG Player from an ARM/Zynq, which is connected to the Artix JTAG interface. Through bitbang the P33 memory of the Artix 200 should then be updated but is not due to errors.
With a different Micron memory mt28gu256aax1e-bpi-x16 (G18) this works without errors. With the P33 memory however we get consistent TDO errors right after programming started. The JTAG player always stops with an error at the same line:
SDR 32 TDI (04900180) ;
SDR 17 TDI (000600) ;
SDR 1036 TDI (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
000000000000000000a9) TDO (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
---> 00000000000000000000000004000000) MASK (0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 <---
SIR 6 TDI (02) ;
SDR 17 TDI (000400) ;
Interestingly, programming the P33 memory via PC and Hardware Manager works without problems. In the same JTAG chain is another FPGA, which we can also update successfully. Our guess is, the JTAG chain, the JTAG player and the P33 memory basically work, but maybe the SVF file was not generated properly, or is not fully compatible with the P33 memory?
We also tried other Vivado versions (2016.3, 2016.4, 2017.2) without success.
Did anybody encounter similar behaviour and maybe found a solution?
02-05-2018 11:36 PM
02-06-2018 05:46 AM
thank you for your reply.
the issue still persists.
The frequency is 500kHz. We tried lowering it further, but it didn't help.
The error occurs also with an SVF file which was created from the Aurora example design. The line where the TDO error happens is 11819 (see attached file).
02-06-2018 03:21 PM
Thanks for the info.
Iam yet to look into the SVF.
Have you used this param before you write out the SVF, if not can you try using this?
set_param xicom.config_chunk_size 0
Please provide complete set of commands you used for SVF generation, starting from creating your hardware.
What happens when you play the SVF using Vivado ?
02-07-2018 12:08 AM
thank you for your suggestion.
We've not yet used this parameter. After creating a new SVF file with this parameter, the TDO error still occurs.
Please find attached our TCL-script for creating SVF files and the newly created SVF file with the config_chunk_size parameter set to 0.
Could you point me into the direction on how to play a SVF file in Vivado? The Hardware Manager seems to only accept bit, rbt and bin files.
02-07-2018 12:14 AM
02-07-2018 01:54 AM
Vivado seems to indicate the same/similar issue:
execute_hw_svf C:/Users/Matrix/Documents/aurora_a200_ex-p33_noverify_config_chunk_size_0.svf INFO: [Labtoolstcl 44-615] Merging header information for SVF file. This may take a while depending on your SVF file size. INFO: [Labtoolstcl 44-548] Creating JTAG TCL script from SVF file. This may take a while depending on your SVF file size. INFO: [Labtoolstcl 44-549] Re-opening target in JTAG mode set current_hw_jtag [get_property hw_jtag [get_hw_target localhost:3121/xilinx_tcf/Digilent/210299A181E0]] INFO: [Labtoolstcl 44-551] Sourcing JTAG TCL script: C:/Users/Matrix/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-4176-rosc-x20174/aurora_a200_ex-p33_noverify_config_chunk_size_0.tcl runtest_hw_jtag: Time (s): cpu = 00:00:02 ; elapsed = 00:05:08 . Memory (MB): peak = 1408.965 ; gain = 0.000 ERROR: [Labtools 27-2255] Output value 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010200000 does not match the tdo option value WARNING: [Labtoolstcl 44-546] Execute SVF failed during JTAG TCL script sourcing INFO: [Labtoolstcl 44-550] Restoring target to original mode execute_hw_svf: Time (s): cpu = 00:00:08 ; elapsed = 00:05:36 . Memory (MB): peak = 1408.965 ; gain = 114.621
Befor running the execute_hw_svf-command, I let Vivado scan the JTAG chain and auto-add the Artix. After that I manually added the Micron P33 memory.
02-07-2018 05:01 AM
Thanks for the check.
can you share the aurora_a200_ex-p33_noverify_config_chunk_size_0.tcl file ?
Can you manually edit the corresponding MASK and set the bits to 00 ( replace FF with 00) for this particular line where it's failing in the SVF and rerun?
02-07-2018 07:55 AM
after setting the corresponding MASK bits to 0x00 in line 11819, a TDO error occured in line 11914. When the bits there where set to 0x00 the next error occurred in line 12009. This then continued for line 12104, 12199, 12294...
I then replaced all MASK bits ending with "000000000000000000000000000000000000000ff00000) ;" with "0000000000000000000000000000000000000000000000) ;". The SVF file (which doesn't include a VERIFY check) now runs through without error, both with the SVF(X)LIB and with execute_hw_svf in Vivado. However the bitstream won't load from the flash. The FPGA Done pin stays low.
The TCL file which was used to create aurora_a200_ex-p33_noverify_config_chunk_size_0.svf is the same as I posted earlier.
02-07-2018 03:57 PM
02-08-2018 12:49 AM
02-08-2018 07:50 PM
Thanks for running the tests. From the experiments looks most likely to be SVF issue, let me check this internally and if i have something useful for you shall share.
Meanwhile is this is critical for you i would advice you open an Service Request so that one of our engineers can dig deep and address your issue.
Sorry couldn't be of much help to you on this.
02-09-2018 06:40 AM
02-15-2018 08:49 PM
I checked around, but nothing concrete to help you on this. But mist likely its due to multiple devices in the JTAG chain.
The alternative way would be for you to have 1:1 FPGA Flash with no additional devices in JTAG chain and check the SVF flow.