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dansci
Observer
Observer
1,042 Views
Registered: ‎07-09-2018

One frame reconfiguration

Hi, I'm dealing with Partial Reconfiguration and Soft Error Mitigation of Kintex Ultrascale and during the development of a design a question concerning this mechanisms arose. Is it is possible to reconfigure via ICAP only the frame for which SEM IP reports an error by providing the Linear Frame Address (LFA)? And by the way, how is LFA associated with what is visible in the device floorplanning? Is it possible to extract somehow the information that for a given LFA we are dealing with a specific Pblock in a project? I tried to find a connection, but I don't see it. I was wondering if LFA translation to Physical Frame Address (PFA) might help in this case, but 6-bits for Row Address is not enough in my opinion or I just don't understand something.
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4 Replies
lowearthorbit
Scholar
Scholar
1,022 Views
Registered: ‎09-17-2018

d,

First, why do you care?

Just use the existing SEM IP feature of frame replace correction.  It is provided, for free, tested and working.

Xilinx* created the SEM IP core just because they (we) were tired of answering questions like yours.

l.e.o.

*Ken Chapman and I created The SEM IP, and as I am no longer with Xilinx, I do not have to answer or advise anyone.  But I do wonder why someone would choose not to use the free and tested solution to do exactly what they describe, if only to learn what feature(s) are missing from the SEM IP core as I still use Xilin FPGAs, and as a customer, I can make requests, especially if they benefit my new employer.

 

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dansci
Observer
Observer
997 Views
Registered: ‎07-09-2018

Dear l.e.o.,

I really appreciate your work on the SEM IP. I do care because, for example, there may be more than one error detected by SEM. Then I have to react at a higher level, at the system level, and I wonder what possibilities I have. Or I might consider using Detect Only mode and then it would be useful to know what to do next after detecting the error.

For the second part of my question, knowing how to link a reported frame (LFA) with a particular module in my application would also allow me to assess how critical this problem is (because we know that SEM has a certain latency time in error detection, in which different things can happen when there is an error in the configuration memory).

I have one more thing I would like to make clear. Maximum Number of Configuration Frames is lower than all configuration frames in the device. I understand that it is not important which frames they are, but it is important that the whole design does not exceed this maximum number of frames? And if you have the time to write briefly why this limitation is, I would be grateful, I'm just curious.

Finally, I want to use SEM, which means that I care about the reliability of the design. And personally I feel better about doing something with high reliability when I know the mechanisms that are responsible for it :)

Regards, Daniel

 

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lowearthorbit
Scholar
Scholar
985 Views
Registered: ‎09-17-2018

d,

It is almost never that you get two non-adjacent upsets.  Just does not happen.  If you use frame replace 100% of upsets are repaired.  If the SEM IP itself is hit is the only way this fails.

You do not need to know what frame, you need to know framne and bit.  That would require a complete map of actual critical bits themselves, injecting faults one by one to find those that break your design (I have never heard of anyone doing that, ever).  I am aware of people doing random fault testing to find out how a design acts, find the architectual vulnerability factor (roughly how many upsetrs it takes to break a design as not all upsets affect the design -- typically only 1 in 20 break a design).

Max number of frames are in the data sheet, and when you create your repair by replace file you will have all type 2 frames in your design.

l.e.o.

 

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pgigliotti_usac
Explorer
Explorer
113 Views
Registered: ‎10-22-2020

Using the SEM Ip core is an issue when going through DO-254

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