07-28-2021 05:32 AM - edited 07-28-2021 05:33 AM
As for PLL dynamic phase shift approach, I have few questions:
1. Could I actually generate a 90 degree phase-shifted clock from CLK_OUT2 using DCM_SP Settings ?
Could I actually generate a 270 degree phase shifted clock from CLK_OUT4 using DCM_SP Settings ?
2. What about PLL_BASE Settings which seems to have the phase shift capability as well ?
07-28-2021 09:17 AM
The PLLs in the Spartan-6 do not have phase shifting capabilities.
In Spartan-6 if you want to use phase shifting, you need to use the DCM. You can cascade both the PLL and DCM if you need the frequency generation capabilities of the PLL as well as the phase shifting of the DCM.
In later technologies (Virtex-6 and onward) the MMCM is a "Mixed Mode Clock Manager" which merges together the features of a PLL (which is analog) and the phase shifting capabilities of the DCM (which is digital), hence the "Mixed Mode".
07-29-2021 01:23 AM - edited 07-29-2021 09:16 PM
When I simulate my design with DCM, I have Warning : Input Clock Period Jitter on instance test_ddr3_memory_controller.ddr3_control.pll_ddr.dcm_sp_inst exceeds 1.000 ns. Locked CLKIN Period = 0.822. Current CLKIN Period = 0.822.
Why PLL DCM could not be locked ?
08-08-2021 07:21 PM - edited 08-08-2021 07:29 PM
For PLL dynamic phase shift, ck_dynamic output is incorrect with respect to udqs_r
Note: I try to read the Xilinx support webpage on dynamic phase shift FAQ, but I still could not find what I want in order to debug the non-working dynamic phase shift.
08-14-2021 07:48 PM - edited 08-14-2021 08:06 PM
ck_dynamic output frequency issue is solved.
I made a mistake in the CLKIN_PERIOD and M/D ratio inside the clocking wizard configuration.
I have attached the wizard-generated pll_tuneable.v file.
From the simulation waveform, it seems that ck_dynamic output is still not 90 degree phase-locked (it is now 180 degree) to incoming udqs_r. Why ?