UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
12,261 Views
Registered: ‎12-06-2010

PROM Configuration for ARTIX-7 FPGA & Reference Schematics

Hi

 

I have a requirement of Artix-7 FPGA (XC7A200T) in my design. I have seen some of the document and i couldnt get the which configuration PROM should be used for Artix-7 FPGA. So, can you please tell me PROM device for XC7A200T?

 

Then, please provide the reference schematics for XC7A200T device.

 

 

Magalingam

Tags (1)
0 Kudos
6 Replies
Highlighted
Instructor
Instructor
12,252 Views
Registered: ‎08-14-2007

Re: PROM Configuration for ARTIX-7 FPGA & Reference Schematics

ug470 Table 1-1 shows the minimum size of configuration PROM as well as the bitstream length for each device.  For the XC7A200T, the bistream length is listed as 77,845,216 bits and the minimum device size is 128 Mbits.

 

Which device you choose may depend on considerations such as how many IO pins you can tolerate losing to configuration and how fast you need the system to come up.

 

For low IO pin-count, typically Master SPI mode is best.  See figure 2-10.

 

For fast startup, Master BPI is best.  See figure 2-14.

 

Note that the schematics are generic for any 7-series parts, however there are some differences between 7-series families, mostly in the types of available IO banks and voltages.

-- Gabor
Adventurer
Adventurer
12,247 Views
Registered: ‎12-06-2010

Re: PROM Configuration for ARTIX-7 FPGA & Reference Schematics

Gabor , Really thank you. I am going to use XC7A200T1FBG484I. It have 285 GPIO. But, i am going to use 270 IO's. Shall i use Master SPI or Slave SPI for configuration device? Then, how to implement multiple Design Revisions (like Rev 0 and Rev 1). I want to load two applications code to FPGA. By selecting the switch i need to configure the particular Design revisions (Either Rev0 or Rev1). Magalingam
0 Kudos
Moderator
Moderator
12,243 Views
Registered: ‎01-15-2008

Re: PROM Configuration for ARTIX-7 FPGA & Reference Schematics

Hello Magalingam,

 

You can use the master spi configuration, there is no slave SPI configuration scheme.

You can use the multiboot scheme to select between two designs, kindly check the following link for the configruation guide, you can check the multiboot section

http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf

 

--Krishna

0 Kudos
Adventurer
Adventurer
12,238 Views
Registered: ‎12-06-2010

Re: PROM Configuration for ARTIX-7 FPGA & Reference Schematics

Krishna, Thank you. So, i can use either G18 or P30 family from Parallel NOR flash memory in Micron.

 

Shall i use synchrounes mode for NOR flash memory on Master Mode BPI?

 

Can you please send me the reference schematics for FPGA-7 series?

 

Now, i am clear on loading different design revisions on FPGA through config flash.

 

 

Magalingam

0 Kudos
Moderator
Moderator
12,236 Views
Registered: ‎01-15-2008

Re: PROM Configuration for ARTIX-7 FPGA & Reference Schematics

Yes, G18F and P30 flashes are supported.

For Micron G18: Non-Mux interface family members are supported. check impact help for the list of flashes supported.

You can check ug470 for BPI synchronous mode support details for config.

It has the BPI interface details.

you can refer to KC705 board files(schematic) for BPI and SPI interface details

http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/boards_and_kits/kintex-7_boards_and_kits/kintex-7_fpga_kc705_evaluation_kit.html

 

--Krishna

0 Kudos
Adventurer
Adventurer
12,232 Views
Registered: ‎12-06-2010

Re: PROM Configuration for ARTIX-7 FPGA & Reference Schematics

Krishna,

Thank you for your support. If i have doubt while designing, i will get back to you.

Magalingam

0 Kudos