UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
560 Views
Registered: ‎08-04-2018

PS accessing

Hi guys, 

 

I am trying to run a simple hello world task. as shown here,

 

http://www.fpgadeveloper.com/2014/07/creating-a-base-system-for-the-zynq-in-vivado.html

 

But I have this

 xili.PNG

I have a vivado and sdk 2016.4. How do i work around this barrier? I have the exact block diagram as shown on the blog. 

0 Kudos
3 Replies
Voyager
Voyager
544 Views
Registered: ‎08-16-2018

Re: PS accessing

No, you don't have the same IP block. Even if apparently the same on the outside, you still need to double click on it and enable the uart.

Adventurer
Adventurer
539 Views
Registered: ‎08-04-2018

Re: PS accessing

ahhh, understoood..

 

ust enabling the UART I/O peripherals is sufficient or should I make some connections too?OK I will try and get back to you. Because there is just the zynq core with M_AXI clk connect to the global clk and nothing else in the BD so.

 

Thanks.

 

 

no more error. Thanks

0 Kudos
Voyager
Voyager
532 Views
Registered: ‎08-16-2018

Re: PS accessing

The PS I/O ports are fixed, no need to place them. 

As far as I remember, the PS has several possibilities for the UART (and other peripherals). You still have to choose the right pins according to your board (check schematic or user guide if you use an Eval Board)

0 Kudos