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Observer zbx5922
Observer
491 Views
Registered: ‎04-16-2014

Parallel Daisy Chain Configuration problem

Hi, I use one flash memory to config two Ultrascale KU115 FPGA, and connect as the UG570 Pg208  'Parallel Daisy Chain Configuration' mode. the two FPGA have two different file.  I have try to build the mcs file , but it did not work (only the first FPGA can be configured, but the second one did not be configed)  .   So, how to build the flash config memory file(mcs) from the two bits file?  Is there any parameters need to be set when generate the two bitstream files and the mcs files ? 捕获.JPG

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7 Replies
Moderator
Moderator
461 Views
Registered: ‎06-05-2013

Re: Parallel Daisy Chain Configuration problem

write_cfgmem should create the correct file for you. Can you share the command which you are using?
In a parallel daisy chain the second bit file is expected to be directly after the first bit file. Refer to the below command!
write_cfgmem -format mcs -interface bpix16 -size 256 -loadbit "up 0 a.bit b.bit" -file design.mcs

Thanks
harshit
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Observer zbx5922
Observer
439 Views
Registered: ‎04-16-2014

Re: Parallel Daisy Chain Configuration problem

thanks. my command is

" Write_cfgmem -format mcs -size 128 -interface BPIx16 -loadbit {up 0x00000000 "c:/bits/rf/bit" "c:/bits/bb.bit"} -checksum -force -file "c:/bits/mcs/test/mcs"  

After Power on,  the first FPGA, which config in Master BPI mode, can load the configure data from the Flash, but the seceond is always failed. The two FPGA configure Done is the connect together, so the first Configure Status Register " CFF_STARTUP_STATE_MACHINE_PHASE" is in state Phase 4 (Release the Done). so the First FPGA  can not work too. 

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Xilinx Employee
Xilinx Employee
434 Views
Registered: ‎08-10-2008

Re: Parallel Daisy Chain Configuration problem

Hi,

If you measure the CSO_B pin of the first FPGA, was it low? Read the STAT of the second one, what did you get?

 

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Observer zbx5922
Observer
427 Views
Registered: ‎04-16-2014

Re: Parallel Daisy Chain Configuration problem

I can see the  Cso_B be low for about 1.5s.  The second FPGA configure register CFG_STARTUP_STATE_MACHINE_PHASE is "000".    the status register value is  " 01110100100000000001111000001100"  .  the "DONE_INTERNAL_SIGNAL_STATUS" bit is "0" .  

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Xilinx Employee
Xilinx Employee
410 Views
Registered: ‎08-10-2008

Re: Parallel Daisy Chain Configuration problem

The STAT indicates the data sent out was ignored by the second FPGA.

There was some issue with iMPACT to generate a MCS for a parallel daisy chain; the workaround is to use command as below:

promgen -w -p mcs -c FF -o output_file -bpi_dc parallel -u 0 device1.bit downstream_device_2.bit

bpi_dc swith can make CSOB command be properly added. Not sure if Vivado had fixed this.

So for this:

1. You mentioned you see CSO_B low. Was it high at first and then low (approx. after data loading of first fpga was finished)?

2. Were data lines still toggling after CSO_B was low?

3. Were the A address lines still togglign after CSO_B low?

I want to check whether CSOB command was working as expected.

 

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Observer zbx5922
Observer
404 Views
Registered: ‎04-16-2014

Re: Parallel Daisy Chain Configuration problem

Thans,  I will try to use iMPACT tool to generate the MCS files. 

answer about the question below 

So for this:

1. You mentioned you see CSO_B low. Was it high at first and then low (approx. after data loading of first fpga was finished)?

 Yes, It is high at first and then be low after the first FPGA finished

2. Were data lines still toggling after CSO_B was low?

yes , it is 

3. Were the A address lines still togglign after CSO_B low?

yes , the address is always togglign, no matter the CSO_B is low and high.

 

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Xilinx Employee
Xilinx Employee
400 Views
Registered: ‎08-10-2008

Re: Parallel Daisy Chain Configuration problem

Behavior seems as expected.iMPACT may not work for a US device but you can have a try.

For a daisy chain, the DONE of the first device is set to pullnone why the second can be set to Drive high or pullnone, leaving the pull up by external resistor. Did you set these correctly?

Besides, set the read mode of the first FPGA to Master BPI Async first.

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