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Observer wanqingxilinx
Observer
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Registered: ‎01-22-2008

Partial Reconfiguration works with JTAG but not Slave SelectMAP

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I have a design with partial reconfiguration partition/modules that works with JTAG link, but not Slave SelectMAP. To make Slave SelectMAP to work, I have set the following 2 properties according the page 119 of Partial Reconfiguration User Guide UG909 (v2018.3) December 5, 2018.

Re:

set_property BITSTREAM.CONFIG.PERSIST Yes [current_design]
set_property CONFIG_MODE {S_SELECTMAP} [current_design]

Any suggestions on what I should do to make ti work? Thanks!

 

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Observer wanqingxilinx
Observer
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Registered: ‎01-22-2008

回复: Partial Reconfiguration works with JTAG but not Slave SelectMAP

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The full bit files generated with setting CONFIG_MODE property to S_SELECTMAP16 before implementation work perfectly with all partial bit files. There is no need to generate bit/byte swapped bin file in this case (using write_cfgmem –format bin). Also, the above mentioned full bit files work also with all partial bit files generated without setting CONFIG_MODE property to S_SELECTMAP16. This seems to say that  CONFIG_MODE property matters for the full bit files only, not partial bit files.

To summarize what was done to make it work:

  1. Added a fpga_pr_reload command for partial bit file loading, which does not assert prog_b.
  2. Remove all reference to the 16 bit LAD bus  in HDL design and constraint file.
  3. set_property BITSTREAM.CONFIG.PERSIST Yes [current_design] before synthesis or implementation
  4. set_property CONFIG_MODE S_SELECTMAP16 [current_design] before implementation

Thanks @iguo @harshit for all the help!

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008

回复: Partial Reconfiguration works with JTAG but not Slave SelectMAP

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Generally the partial bit was not accepted by FPGA. 

How did you send the initial bit out? By SMAP as well? For SMAP interface, make sure you have the correct data format, aka, byte swapping.

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Observer wanqingxilinx
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Registered: ‎01-22-2008

回复: Partial Reconfiguration works with JTAG but not Slave SelectMAP

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iguo,

Could you please elaborate on "Generally the partial bit was not accepted by FPGA"?

A. When I say it works with JTAG, I had to load the full bit file with Slave SelectMAP first, then load the partial bit files (for dynamic reconfiguration) via JTAG. I could see the reconfigured module function was working correctly.

B. When I do it all with Slave SelectMAP, both full and partial bit file loadings do not give any error. However, I do not see the effect of reconfigurable module in the partial bit file. It looks like that nothing has happened. It seems like partial bit file was not accepted by FPGA.

Since A works, I suppose there is no problem with the bit files genreated.

Actually, I followed the instruction on page 119 of Partial Reconfiguration, UG909 (v2018.3) December 5, 2018 to set the following properties before implementation in TCL console:

set_property BITSTREAM.CONFIG.PERSIST Yes [current_design
set_property CONFIG_MODE {S_SELECTMAP} [current_design]

It still did not make any difference. Have I missed anything and is there way to debug this? Thanks!

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008

回复: Partial Reconfiguration works with JTAG but not Slave SelectMAP

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What I mean was the FPGA did not see your partial bit feeding into SMAP, in other word, the partial data was totally ignored by FPGA.

The difference between JTAG and SMAP is that the latter is parallel port. You should guarantee the data sent out have the correct sequence. Check the byte/bit swap section on any Config User guide. If you do this wrong, all the data will be ignored by FPGA.

Partial has no much sign telling you your data is accepted or not. You must either trigger an ABORT or monitor ICAP'O port to check your partial status, anyhow, both of them were not easy for beginners. So check if you have the correct data bytes is always the first step.

 

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Observer wanqingxilinx
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Registered: ‎01-22-2008

回复: Partial Reconfiguration works with JTAG but not Slave SelectMAP

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Thanks iguo for the explanation.

I generated both the full and partial bit file with the project flow using Vivado IDE. Since both full and partial bit file loading are through the same SMAP and full bit file loading works, I suppose the partial bit file would have same the byte and bit ordering as that of full bit file. Is this correct?

Still, I would like to check to see if partial bit file's byte/bit ordering has a problem. How do I do that, by looking at the bitstream geneation properties, by looking at the bit file's hex dump? Could you please guide me through this? And, how should I resovle the problem at the bitstream generation side since doing it a microprocessor side would involve more work as I see it. Thanks very much for your help.

 

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Observer wanqingxilinx
Observer
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Registered: ‎01-22-2008

回复: Partial Reconfiguration works with JTAG but not Slave SelectMAP

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@iguo

Page 88 of 7 Series FPGAs Configuration User Guide UG470 (v1.13.1) August 20, 2018 says:

Then a special 32-bit synchronization word (0xAA995566) must be sent to the configuration logic. The synchronization word alerts the device to upcoming configuration data and aligns the configuration data with the internal configuration logic. Any data on the configuration input pins prior to synchronization is ignored, except the “Bus Width Auto Detection” sequence.

So, I did a hex dump on the bit files. Looking at the synch word, it looks to me that they are of the same bite/byte order. Any other ideas about things to check?

Full bit file 1:
% od -x fpga_v2_0114_1_incr2.bit | more
:
0000240 0000 bb11 2200 44ff ffff ffff ffff ffaa
0000260 9955 6620 0000 0030 0220 0100 0000 0030
:

Full bit file 2:
% od -x fpga_v2_0114_1_incr3.bit | more

:
0000240 0000 bb11 2200 44ff ffff ffff ffff ffaa
0000260 9955 6620 0000 0030 0220 0100 0000 0030
:


Full bit file 3:
% od -x fpga_v2_0114_1_incr4.bit | more
:
0000240 0000 bb11 2200 44ff ffff ffff ffff ffaa
0000260 9955 6620 0000 0030 0220 0100 0000 0030
:


Partial Bit File 1:
% od -x fpga_v2_0114_1_incr3_pr.bit | more
:
0000260 1122 0044 ffff ffff ffff ffff aa99 5566
0000300 2000 0000 3000 8001 0000 0007 2000 0000
:

Partial Bit File 2:
% od -x fpga_v2_0114_1_incr3_pr.bit | more
:
0000260 1122 0044 ffff ffff ffff ffff aa99 5566
0000300 2000 0000 3000 8001 0000 0007 2000 0000
:

Partial Bit File 3:
% od -x fpga_v2_0114_1_incr4_pr.bit | more
:
0000260 1122 0044 ffff ffff ffff ffff aa99 5566
0000300 2000 0000 3000 8001 0000 0007 2000 0000
:

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Observer wanqingxilinx
Observer
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Registered: ‎01-22-2008

回复: Partial Reconfiguration works with JTAG but not Slave SelectMAP

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Hi @iguo

Sorry that I forgot to answer your question directly on "How did you send the initial bit out? By SMAP as well?".

A sucessful case is this: Load full bit file (initial bit file) via Slave SelectMAP by a microprocessor; Load partial bit file via JTAG.

 

The failed but desired case is this: Load both full and partial bit files via Slave SelectMAP by a microprocessor.

 

ICAP is not used in the design. A 16-bit external Slave SelectMAP link is to be used for both full and partial bit file loading -- this is our desired solution. Thanks.

 

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Xilinx Employee
Xilinx Employee
592 Views
Registered: ‎08-10-2008

回复: Partial Reconfiguration works with JTAG but not Slave SelectMAP

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The file is not swapped. Use write_cfgmem to generate .bin file and make CPU to play the bin file:

when you use write_cfgmem, add this switch: -interface SMAPx16. Example:

write_cfgmem -format BIN -interface SMAPx16 -loadbit "up 0x0 <partial_bitfile>”

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Moderator
Moderator
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Registered: ‎06-05-2013

回复: Partial Reconfiguration works with JTAG but not Slave SelectMAP

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Just to update the thread.
After using the S_SELECTMAP16 constraints within the design everything worked for them. Initially they were using the x8 bus constraint which wasn't setting the bus correctly.

Thanks
Harshit
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Observer wanqingxilinx
Observer
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Registered: ‎01-22-2008

回复: Partial Reconfiguration works with JTAG but not Slave SelectMAP

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The full bit files generated with setting CONFIG_MODE property to S_SELECTMAP16 before implementation work perfectly with all partial bit files. There is no need to generate bit/byte swapped bin file in this case (using write_cfgmem –format bin). Also, the above mentioned full bit files work also with all partial bit files generated without setting CONFIG_MODE property to S_SELECTMAP16. This seems to say that  CONFIG_MODE property matters for the full bit files only, not partial bit files.

To summarize what was done to make it work:

  1. Added a fpga_pr_reload command for partial bit file loading, which does not assert prog_b.
  2. Remove all reference to the 16 bit LAD bus  in HDL design and constraint file.
  3. set_property BITSTREAM.CONFIG.PERSIST Yes [current_design] before synthesis or implementation
  4. set_property CONFIG_MODE S_SELECTMAP16 [current_design] before implementation

Thanks @iguo @harshit for all the help!

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