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Visitor
Visitor
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Registered: ‎12-23-2018

Partial Reconfiguration

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Hi,

If i create two or more partial reconfigurable block in the floorplanning in Vivado with same physical size and including same FPGA resources. Will the generated bit files describe the two regions in the same way? Can i load the same configuration to the two partial regions even if a configuration synthesised and implemented for one region in Vivado ?

Thanks in advance,

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008

No you cannot do this.

The two regions actually have different coordinates, and the partial bitstreams generated will identify the coordinates.

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Xilinx Employee
Xilinx Employee
928 Views
Registered: ‎08-10-2008

No you cannot do this.

The two regions actually have different coordinates, and the partial bitstreams generated will identify the coordinates.

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629 Views
Registered: ‎05-17-2018

To be sure I understood the answer, it means that the partial binary is generated for the couple "Reconfigurable Module + Reconfigurable partition" and if  a Reconfigurable Module can be placed in multiple Reconfigurable Partitions we will have for this unique Reconfigurable Module multiple partial binaries?

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Xilinx Employee
Xilinx Employee
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Registered: ‎11-17-2008
Yes, exactly. Even though the function of the module is logically identical, the physical implementation, both of the module in a unique location as well as the static design that surrounds it, will be completely unique. A unique bitstream for this unique location is required. Partial bitstreams are not relocatable.
thanks,
david.
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Visitor
Visitor
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Registered: ‎12-23-2018

If the function of the module is logically identical, why it's surrounddings are different ? Can't i change just location information within bitstream file ? Why ?

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Xilinx Employee
Xilinx Employee
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Registered: ‎11-17-2008

@aniltirli,

Because the partial bitstream contains more than the implementation of the dynamic function.  The programming in the partial bitstream includes parts of the static design, from clock signals and flyovers to static functions on the periphery of the dynamic region.  While the partial bitstream only changes the logical function of that module, the Vivado tools are free to overlap (safely, of course) the dynamic and static parts of the design to improve design performance.  In order for a partial bitstream to be relocatable, everything about the static region around it would need to be absolutely identical, and that would be incredibly limiting for design performance.  Take a look at the "expanded routing" capability in UG909 to see how the regions overlap.

thanks,

david.

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