09-26-2019 06:31 PM
I'm developing a way to configure a PR using a clear partial bit stream file to ICAPE3 using Ultrascale+ with an encrypted static logic.
We develop the encrypted static bit stream file and we would like to allow the user to reconfigure his partition, nothing else.
09-27-2019 12:46 PM
09-27-2019 01:43 PM
Thanks Harshit but that doesn't answer my question.
A valid CRC doesn't mean the bitstream is compatible with my static logic and won't corrupt my static logic.
I mentionned pr_verify too.
09-27-2019 03:25 PM
09-27-2019 09:34 PM
Basically, I don't have any control over the partial bit file generation.
I was more thinking about reading the bit file sent inside the FPGA to check if the elements are contained inside the pBlock I defined for that partition. They still might corrupt the logic but that's already a good pre-check for us.