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Visitor
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Registered: ‎02-04-2020

Pmod JC coneection error

I won BASYS 3 and i wanted to connect pmod encoder to my JC pin 1 to 6, but when i generate the bitstream

i get this error:

 

  • [DRC NSTD-1] Unspecified I/O Standard: 2 out of 33 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: A, and B.
  • [DRC UCIO-1] Unconstrained Logical Port: 2 out of 33 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: A, and B.

why

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Registered: ‎06-21-2017

The messages are telling you that two of your IO signals are not assigned to pins of the FPGA and two signals, probably the same ones, do not have an IO standard assigned.  The Placer report will tell you what IO signals are assigned to which locations and what IO standards you have assigned to them.  An asterisk (*) will tell you that no value was assigned by you and these are the signals you need to add to your xdc file.

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Visitor
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Registered: ‎02-04-2020

my solution was to remove the commented #sch name" on the xdc file.

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