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Visitor
Visitor
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Registered: ‎09-27-2019

Power fo the FPGA BANK

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when using the FPGA,  the unused Bank , should I power ? 

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-06-2018

Re: Power fo the FPGA BANK

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Hi @zhanghefu ,

Yes, you will save some static power by not powering unused Banks and IO's in the corresponding bank.

Functionality and performance remains same, since VCCINT voltage you are giving to FPGA is constant value.

Leaving the VCCO pins of unused I/O banks floating reduces the level of ESD protection on these pins and the I/O pins in the bank. For maximum ESD protection in an unused bank, all VCCO pins in that bank should be connected together to the same potential, whether that be a valid VCCO voltage, or a floating plane. I/O pins are also recommended to be connected to the same potential as VCCO, or they can be left floating.

For more information refer PCB Guidelines userguide of corresponding Device family.

Hope this helps.

Regards,
Deepak D N
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Mentor
Mentor
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Registered: ‎04-26-2015

Re: Power fo the FPGA BANK

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You don't have to; it'll save a little bit of power if you leave the unused bank un-powered.

 

On the other hand, it's a lot easier to do modifications to the board if all banks are powered (so you have those pins available if required).

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Visitor
Visitor
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Registered: ‎09-27-2019

Re: Power fo the FPGA BANK

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Yeah, In order to reduce the power consumption, I want to know the unused FPGA Bank, Can I power down the bank? for example, BANK15, BANK16,BANK17 I use, but the BANK31, BANK32, BANK33 I do not use, if I power down the BANK31, BANK32,BANK33, if the FPGA function and performance is influenced?

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-06-2018

Re: Power fo the FPGA BANK

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Hi @zhanghefu ,

Yes, you will save some static power by not powering unused Banks and IO's in the corresponding bank.

Functionality and performance remains same, since VCCINT voltage you are giving to FPGA is constant value.

Leaving the VCCO pins of unused I/O banks floating reduces the level of ESD protection on these pins and the I/O pins in the bank. For maximum ESD protection in an unused bank, all VCCO pins in that bank should be connected together to the same potential, whether that be a valid VCCO voltage, or a floating plane. I/O pins are also recommended to be connected to the same potential as VCCO, or they can be left floating.

For more information refer PCB Guidelines userguide of corresponding Device family.

Hope this helps.

Regards,
Deepak D N
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