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Observer
Observer
931 Views
Registered: ‎05-10-2018

Problem signal FCS_B don't go Low

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Hi,

 

I'm now trying to configure Artix-7 on the new board designed by ourselves.

But I couldn't download mcs file into ROM at JTAG Only mode (M[2:0]=101)with above messsages.

# in vivado HW manager, FPGA device(xc7a100t) itself is detected.

 

[Labtools 27-2251] Unable to read device properties. Please make sure that the proper configuration memory part is selected.

 

So I configured the SPI ROM by ROM writer and mounted on the board. Then tryed to start the system at Master SPI mode(M[2:0]=001), but I couldn't either..

 

- Checking the waveform, FCS_B is always Hi.(abnormal)

  PROGRAM_B and INIT_B go Low and soon after back to Hi (normal)

- SPI ROM is N25Q128 3.3V

- Supply power to FPGA and SPI ROM is okay. 

- ROM date is created with SPIx1 setting (generate bitstream)

- compile machine vivado 2016.2

 

Coulde you tell us if anyone have any idea about this issue?

 

register value at SPI mode is as following.

 

Name Value
CLASS hw_device
DID jsn-DLC10-0000131cfe7d01-13631093-0
IDCODE 00010011011000110001000010010011
IDCODE_HEX 13631093
INDEX 0
IR_LENGTH 6
IS_SYSMON_SUPPORTED true
MASK 00001111111111111111111111111111
MASK_HEX 0FFFFFFF
NAME xc7a100t_0
PART xc7a100t
PROBES 
FILE 
PROGRAM 
DPA_COUNT 0
DPA_MODE 
DPA_PROTECT false
FILE 
HW_BITSTREAM 
HW_CFGMEM 
HW_CFGMEM_BITFILE 
HW_CFGMEM_TYPE 
IS_AES_PROGRAMMED false
IS_RSA_PROGRAMMED false
IS_SUPPORTED true
OPTIONS 
READBACK_FILE 
REGISTER 
BOOT_STATUS 00000000000000000000000000000000
BIT00_0_STATUS_VALID 0
BIT01_0_FALLBACK 0
BIT02_0_INTERNAL_PROG 0
BIT03_0_WATCHDOG_TIMEOUT_ERROR 0
BIT04_0_ID_ERROR 0
BIT05_0_CRC_ERROR 0
BIT06_0_WRAP_ERROR 0
BIT07_0_SECURITY_ERROR 0
BIT08_1_STATUS_VALID 0
BIT09_1_FALLBACK 0
BIT10_1_INTERNAL_PROG 0
BIT11_1_WATCHDOG_TIMEOUT_ERROR 0
BIT12_1_ID_ERROR 0
BIT13_1_CRC_ERROR 0
BIT14_1_WRAP_ERROR 0
BIT15_1_SECURITY_ERROR 0
BIT16_RESERVED 0000000000000000
CONFIG_STATUS 01010000000000000001100100001100
BIT00_CRC_ERROR 0
BIT01_DECRYPTOR_ENABLE 0
BIT02_PLL_LOCK_STATUS 1
BIT03_DCI_MATCH_STATUS 1
BIT04_END_OF_STARTUP_(EOS)_STATUS 0
BIT05_GTS_CFG_B_STATUS 0
BIT06_GWE_STATUS 0
BIT07_GHIGH_STATUS 0
BIT08_MODE_PIN_M[0] 1
BIT09_MODE_PIN_M[1] 0
BIT10_MODE_PIN_M[2] 0
BIT11_INIT_B_INTERNAL_SIGNAL_STATUS 1
BIT12_INIT_B_PIN 1
BIT13_DONE_INTERNAL_SIGNAL_STATUS 0
BIT14_DONE_PIN 0
BIT15_IDCODE_ERROR 0
BIT16_SECURITY_ERROR 0
BIT17_SYSTEM_MONITOR_OVER-TEMP_ALARM_STATUS 0
BIT18_CFG_STARTUP_STATE_MACHINE_PHASE 000
BIT21_RESERVED 0000
BIT25_CFG_BUS_WIDTH_DETECTION 00
BIT27_HMAC_ERROR 0
BIT28_PUDC_B_PIN 1
BIT29_BAD_PACKET_ERROR 0
BIT30_CFGBVS_PIN 1
BIT31_RESERVED 0
COR0 
BIT09_MATCH_CYCLE 111
BIT00_GWE_CYCLE 100
BIT03_GTS_CYCLE 101
BIT06_LOCK_CYCLE 111
BIT12_DONE_CYCLE 011
BIT15_SSCLKSRC 00
BIT17_OSCFSEL 000000
BIT23_SINGLE 0
BIT24_DRIVE_DONE 0
BIT25_DONE_PIPE 0
BIT26_RESERVED 0
BIT27_PWRDWN_STAT 0
BIT28_RESERVED 0000
COR1 
BIT00_BPI_PAGE_SIZE 00
BIT02_BPI_1ST_READ_CYCLE 00
BIT04_RESERVED 0000
BIT08_RBCRC_EN 0
BIT09_RBCRC_NO_PIN 0
BIT10_RESERVED 00000
BIT15_RBCRC_ACTION 00
BIT17_PERSIST_DEASSERT_AT_DESYNC 0
BIT18_RESERVED 00000000000000
EFUSE 
DNA_PORT 024D44163B9085C
FUSE_CNTL 00C0
FUSE_DNA 3A109DC6822B2413
FUSE_KEY 0000000000000000000000000000000000000000000000000000000000000000
FUSE_USER 00000000
IR 010001
BIT0_ALWAYS_ONE 1
BIT1_ALWAYS_ZERO 0
BIT2_ISC_DONE 0
BIT3_ISC_ENABLED 0
BIT4_INIT_COMPLETE 1
BIT5_DONE 0
TIMER 00000000
BIT00_TIMER_VALUE 000000000000000000000000000000
BIT30_TIMER_CFG_MON 0
BIT31_TIMER_USR_MON 0
USERCODE ffffffff
USR_ACCESS 0
WBSTAR 00000000
BIT00_START_ADDR 00000000000000000000000000000
BIT29_RS_TS_B 0
BIT30_RS 00
UNKNOWN_DEVICE false
USER_CHAIN_COUNT 4
XSDB_USER_BSCAN 1,3

 

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Highlighted
Observer
Observer
1,008 Views
Registered: ‎05-10-2018

Because of mistake of resistor value, ROM got broken.

After replace of ROM, it works normally.

View solution in original post

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Highlighted
Observer
Observer
881 Views
Registered: ‎05-10-2018


Sorry, I've mistaken the Pull-up resistor value of FCS_B signal. It was so small that FPGA couldn't drive this signal low.

After changing the resistor, FCS_B went to Low.

 

But still can't start the system at Master SPI mode(M[2:0]=001).

Data signal from FPGA to ROM doesn't work at all(always low)

 

And still I can't download mcs file into ROM at JTAG Only mode (M[2:0]=101).

 

Please could you tell us if anyone have any idea about this issue?

 

 

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Highlighted
Observer
Observer
1,009 Views
Registered: ‎05-10-2018

Because of mistake of resistor value, ROM got broken.

After replace of ROM, it works normally.

View solution in original post

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