09-13-2020 02:10 AM - edited 09-13-2020 02:10 AM
It is 2020, re-quote it is 2020!!
In the following question, i will like to summarize all the possible headache questions from of previous posts.
Using EMCCLK for what purpose? - Speed up the flash time.
How to setup? - Using the XDC constrains.
Right it looks very simple. However not really.
Read all the datasheet as much as you like.
It makes not different with or without the EMCCLK connected to the FPGA.
In the following case, i will use the Kintex 7 as a common and good example.
The development boards i am using is Kintex 7 FFG676 and FFG900.
Conenct emcclk with 50MHz OSC. setting the emcclk to en with XDC, using JTAG 30MHz programmer.
Internal oscillator QSPI MT25Q256 max 133MHz, 51s programming time with erase and flash in.
Emcclk QSPI MT25Q256 max 133MHz, 51s programming time with erase and flash in.
BPI internal oscillator 37s programming time with erase and flash in.
BPI emcclk 37s programming time with erase and flash in.
So why and why do we need to add OSC to emcclk?
Any thing i am doing wrong? Why i see post that user are posting with such problem but no solution at all?
I hope this post settle all other once for all.
09-16-2020 01:50 PM
09-17-2020 06:48 AM - edited 09-17-2020 06:50 AM
Right! With all the responses from the web and headaches that previous developer had go through. How do we see it wont reduce the programming time from the documents?
I assume not highlighting means not a feature which leads to wont contributing. AKA it will not reduce the programming time but only the redo timing.
I highly understand the document goals are to reduce load time to achieve PCIe initial timing or other RTOS requirements.
However, where and which page(s) or line(s) told us it only affecting the load time but not the programming time?
That the problem i am trying to point out (Of cause i may misreading some important infos.
Please tell us from BPI and SPI doucments.