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Explorer
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Registered: ‎05-25-2016

QSPI FLASH boot failed occasionally

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I'm using a Xilinx XC7K325T FPGA. The SPI Boot Device is a N25Q128 Flash. The boot mode is master SPI x 4. The QSPI FLASH boot failed occasionally. The DONE signal is not going high while boot failed. When looking at the SPI Signals I can see the SCLK ( apprx. 3 MHZ) but no MOSI signal. It seems that no read command was sent from FPGA.

I have checked the power-up sequence, and no problem found.

Could anyone help me?

Thanks in advance!

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Explorer
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Registered: ‎05-25-2016

Re: QSPI FLASH boot failed occasionally

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Thanks everyone!
The problem was solved.
It is due to the gap between power recycle is too short. The voltage on the capacitor of VCCO 3.3V can not be released immediately, which lead to the M[2:0] PINs sampling error.

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Scholar
Scholar
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Registered: ‎04-26-2012

Re: QSPI FLASH boot failed occasionally

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@mage  "The QSPI FLASH boot failed occasionally. <snip>  It seems that no read command was sent from FPGA"

If you have a JTAG cable connected with an instance of hw_server running, SPI boot cycles can be disrupted by software polls of the JTAG registers upon board powerup.

The following AR describes the problem and gives some Tcl workarounds if you need to keep the JTAG cable connected for debug:

  AR# 66954 Intermittent configuration failures can occur when the FPGA is power cycled and the programming cable is connected.

( I have also found that switching to the fastest SPI configuration clock rate makes this much less likely to happen, at least when using a smaller 7K160T )

-Brian

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Registered: ‎05-25-2016

Re: QSPI FLASH boot failed occasionally

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Thanks for your reply. There is no JTAG cable connected to the FPGA during power up. 

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Registered: ‎01-22-2015

Re: QSPI FLASH boot failed occasionally

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@mage

     When looking at the SPI Signals I can see the SCLK ( apprx. 3 MHZ) but no MOSI signal..
This could indicate that the FPGA is not reading M[2:0] pins correctly, which tell the FPGA to use Master-SPI configuration mode (see Table 2-1 in UG470). So, check that you have reliable and correct connections for M[2:0]. While you’re at it, again verify your connections (and pullup resistors) agree with Fig 2-14 in UG470. In addition to M[2:0], pay special attention to the CFGBVS connection and carefully read the description of CFGBVS found in Table 2-4 of UG470.

Does your oscope show any activity on FCS_B line?

We also use Kintex-7 and N25Q128 (or replacement MT25QL128) flash in SPIx1 mode, which has been very reliable.  You might try using the simpler Master-SPIx1 mode, since connections for x1 and x4 mode are similar (compare Figs 2-12 and 2-14 in UG470).  

Mark

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Registered: ‎05-25-2016

Re: QSPI FLASH boot failed occasionally

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Thanks!

I can see FCS-B activity,it seems worked well.

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Registered: ‎01-22-2015

Re: QSPI FLASH boot failed occasionally

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If you are sure that M[2:0]=001, then activity on MOSI/D[00] should soon follow activity on FCS_B as shown in Fig 2.13 of UG470. If you are not seeing this then try removing the flash part from the board. If you then see activity on FCS_B and MOSI/D[00] then perhaps flash part is damaged and needs to be replaced. Flash, N25Q128, is now an End-Of-Life part but can be replaced by MT25QL128.

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Moderator
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Registered: ‎06-05-2013

Re: QSPI FLASH boot failed occasionally

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Please share the following:
-- Vivado Version
-- Status registers during failure. You can connect the JTAG back and read the status registers.
-- bitgen properties : Open implemented design & run the below command:
Report_property -all [current_design]
Thanks
Harshit
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Explorer
Explorer
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Registered: ‎05-25-2016

Re: QSPI FLASH boot failed occasionally

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Thanks everyone!
The problem was solved.
It is due to the gap between power recycle is too short. The voltage on the capacitor of VCCO 3.3V can not be released immediately, which lead to the M[2:0] PINs sampling error.

View solution in original post

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