05-05-2020 11:45 PM
I'm using a system on board device. It consists of a FPGA Spartan 7 (XC7S50CSGA324) with external QSPI Flash (MX25L12833F) and a Microcontroller (STM32F746IG) from ST.
The Microcontroller is linked to the FPGA by a SRAM FMC Memory Interface. When I load a bitstream via JTAG to the FPGA the FMC Memory Interface runs perfectly. I case of doing the configuration by the external flash the FMC Interface doesn't run anymore.
My Question is: What is the different of the I/O pin state during configuration when I use JTAG or Bitstream by external Flash? Is there any default behavior or may there is any setup I can choose?
05-12-2020 08:23 PM
First of all, was the configuration by QSPI successful? DONE pin high? Can you read out a correct STAT register value?
Then, JTAG and SPI configuration make use of different config-related pins, so check if any pin in bank14 and bank 15 connected or affect the FMC card.
Is the MCS file you used for flash generated from the same bit file? For non config-related pins, one XDC named 'bitstream.config.unusedpin' can control the status of all unused I/Os - check if you connect this kind of I/O to the FMC and if you have different settings for them when use JTAG and MCS.
05-13-2020 12:05 AM
Thank you for your help.
First: QSPI configuration was successful, the DONE pin is high after loading and I have some blinking LEDs on other pins so I can see that the FPGA runs. I have already checked this before. But I've never readout any STAT register.
Then: FMC Interface is fully connected to bank 15 and some pins connected to bank 14. But in my oppinion no config realted pin is used. I have attached my xdc file, may you can have a look on it.