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Registered: ‎11-29-2019

Qspi Flash memory

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Hi,

I am doing qspi flash memory in kc705 ,i had successfully read and write from the flash on dq0,dq1 lines respectively.

But now I tried using in dual mode,expect the read data from the flash everything is working fine,at the time where the data from the flash has to appear there both dq0,dq1 lines are high and not showing any output.

I had made the configuration as 

set_property CONFIG_MODE SPIx4 [current_design].

Is it correct or i need to change it to sp*2.

But what i need is qspi where the read from the flash appears on both dq0, dq1 lines while dq2,dq3 are pull up.

Thanks in advance,

Regards,

Jahnavi.

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Registered: ‎01-22-2015

@jahnavijanu.y 

During initial testing, please try to make your SPIx4 interface work at a slow clock speed (eg. 10MHz) – and not 100MHz!

The general method that you used in <this post> for the SPIx1 interface can also be used for the SPIx4 interface.

That is, you first create a pacing clock, CLK_P=100MHz, and use an SPI clock, CLK_SPI=10MHz.  As you did with the SPIx1 interface, you will occasionally pause for “5 cycles of CLK_P”  to ensure that your interface satisfies timing “by design”.   

Is this the approach that you are using?

Please note that a 100MHz clock for SPI is very fast!  You will probably not achieve SPI communication at 100MHz using the “by design” approach to SPI communications that we have been discussing.

However, flash erase/write is typically a slow operation – especially with NOR flash like the N25Q128A.  This slow speed is not a result of slow SPI communications – rather it is the nature of flash memory.  That is, sending a write command or an erase command over the interface can take less than a microsecond – but you must then wait milliseconds for flash to respond to the command (see Erase and Program “cycle time” in Table 38 of the N25Q128A datasheet).

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Registered: ‎01-22-2015

@jahnavijanu.y 

From your <previous post>, I understand that your configuration for the FPGA includes HDL that you created to read/write the N25Q128A flash on the KC705 board.   I also understand that your HDL can now successfully read/write the flash in SPIx1 mode.  Congratulations!

In order to read/write the flash in SPIx4 mode, your HDL must tell the N25Q128A to change from SPIx1 mode to SPIx4 mode (aka Quad-SPI).  As described in Table 8 of the N25Q128A, this is done by using the WRITE ENHANCED VOLATILE CONFIGURATION REGISTER command to set bit 7 equal to 0 in the Enhanced Volatile Configuration Register.  See Table 14, Table 16, and Fig. 12 in the N25Q128A datasheet for more information.

Mark

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Registered: ‎11-29-2019

Thanks for the reply,

I made the WRITE ENHANCED VOLATILE CONFIGURATION REGISTER command to set bit 7 equal to 0 in the Enhanced Volatile Configuration Register.  But even then i can't read any data it is showing 1 on both dq0,dq1 lines.

Thanks in advance,

Regards,

Jahnavi.

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Registered: ‎01-22-2015

@jahnavijanu.y 

In SPIx1 mode, DQ0 and DQ1 of the N25Q128A flash are unidirectional ports (ie. DQ0 was always an input and DQ1 was always an output). 

In SPIx4 (Quad IO) mode, DQ3, DQ2, DQ1, DQ0 (aka DQ[3:0]) are bidirectional ports as described in Table 1 of the N25Q128A datasheet.  Therefore, on each of these ports you will need to instantiate the IOBUF component (pg 394 of UG953) and declare the ports as bidirectional in your design (eg. use inout in VHDL).

IOBUF.jpg

Table 23 and Fig 21 of the N25Q128A datasheet describe the SPIx4 (Quad IO) Read Command.  During the first part of this command (while Command and Address are being sent), DQ[3:0] are inputs to flash.  During the second part of the command (while Data is being sent), DQ[3:0] are outputs from flash.  Your custom HDL will need to control the T-pin of IOBUF to ensure that DQ[3:0] are in the correct state (input or output) during each part of the Read Command.

N25Q128A_quad_io.jpg

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Thank you for the reply,

I had made these as inouts and connected to the iobuf even though i am still getting the output is like that.

Except that everything is going correctly

Thanks in advance,

Regards,

jahnavi.

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Registered: ‎01-22-2015

@jahnavijanu.y 

Although not shown in Fig 21 of the N25Q128A datasheet, you must also control the flash chip select (S#) during Read Memory operations as described on pg 40 of the datasheet.

To test your HDL, are you first writing to a memory location in flash and then reading from the same memory location?

Note that the Write Enable command (pg 49 of datasheet) must be sent to flash before you can Erase or Write to flash.  Also, you must erase a memory location in flash before you can write to it.  When you erase a memory location in flash then all bits of the memory location are set equal to 1.

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Registered: ‎11-29-2019

Thank you for the reply,

I made the chip selct bit to low until the read operation is finished.

I wrote to the address and i am trying to read from the same address,and i also erase the memory and then i program it.

My clk frequency is 100mhz, and i saw in the datasheet of table 13 it is showing some frequency of 108, do i need to change the input clock to 108?

Thanks in advance,

Regards,

Jahnavi.

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Registered: ‎01-22-2015

@jahnavijanu.y 

During initial testing, please try to make your SPIx4 interface work at a slow clock speed (eg. 10MHz) – and not 100MHz!

The general method that you used in <this post> for the SPIx1 interface can also be used for the SPIx4 interface.

That is, you first create a pacing clock, CLK_P=100MHz, and use an SPI clock, CLK_SPI=10MHz.  As you did with the SPIx1 interface, you will occasionally pause for “5 cycles of CLK_P”  to ensure that your interface satisfies timing “by design”.   

Is this the approach that you are using?

Please note that a 100MHz clock for SPI is very fast!  You will probably not achieve SPI communication at 100MHz using the “by design” approach to SPI communications that we have been discussing.

However, flash erase/write is typically a slow operation – especially with NOR flash like the N25Q128A.  This slow speed is not a result of slow SPI communications – rather it is the nature of flash memory.  That is, sending a write command or an erase command over the interface can take less than a microsecond – but you must then wait milliseconds for flash to respond to the command (see Erase and Program “cycle time” in Table 38 of the N25Q128A datasheet).

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Registered: ‎11-29-2019

Thank you so much for the reply,

Now the code is working fine on kc705 in both dual and quad mode . i made a  mistake while configuring the registers.

once again thank you so much for your advice until now, i had understand spi working on fpga in a better way.

Regards,

jahnavi.

 

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