cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
934 Views
Registered: ‎11-29-2019

Qspi flash memory

Jump to solution

Hi,

I wwas trying to programming the qspi flash memory in kc705 board.The tool I'm using is vivado version 2018.3

1)  I tried connecting the dqo ,dq1,dq2,dq3 pins of my spi master to p24,r25,r20,r21,and select signal to u19

And i connected the spi generated sclk to the startup2 primitive  userclk( but in startup2 primitive, does it generate the cclk frequency as the input frequency or it will change the frequency,is it just connecting the sclk to the cclk pin or is it generating any other clock depending on the sclk)

Is it correct or do i need to change any pins?

2)As for reset i couldn't figure out how can i generate internally,i checked and found somewhere they are using eos of startup2 primitive for this does it work my reset is active low.can i connect the reset the eos?

3) how can i check whether the data is passed into the flash successfully or not , does i need to instantiate ila and check or is there any method for this?

Thanks in advance,

Jahnavi

0 Kudos
1 Solution

Accepted Solutions
Highlighted
605 Views
Registered: ‎01-22-2015

@jahnavijanu.y 

An oscilloscope is electrical test equipment that allows you to probe and see electrical signals on your KC705 board.  If you don’t have one in your laboratory then maybe you can borrow one from the electrical technicians in your organization.

It appears that you have found software that does SPI communication and you are trying to make sense of it.  However, SPI communication is quite simple.  You may find it easier to develop your own SPI communication software(HDL) rather than trying to understand someone else’s software. 

If you want to develop your own SPI communication HDL, then I recommend you treat the SPI clock, CLK_SPI, as an ordinary signal – and not generate it using the clocking wizard.  I will show you what I mean later.  Next, use the clocking wizard to create a fast pacing clock, CLK_P. 

The 12 steps below shown how your own HDL (in SPIx1 mode) might work for the N25Q128A “Write Enable” command, when CLK_P=100MHz and CLK_SPI=C=10MHz.

N25Q128A_write_enable.jpg

  1. Set CLK_SPI=C=1. Set S#=1.  <<note how CLK_SPI is assigned values in the same way you assign values to S#
  2. Pause for 5 cycles of CLK_P  <<note that 10 cycles of CLK_P is equal to one cycle of CLK_SPI
  3. Set S#=0
  4. Pause for 5 cycles of CLK_P
  5. Simultaneously set DQ0=0 and set CLK_SPI=0
  6. Pause for 5 cycles of CLK_P
  7. Set CLK_SPI=1
  8. Pause for 5 cycles of CLK_P
  9. Simultaneously place another bit value on DQ0 and set CLK_SPI=0
  10. Repeat steps 6-9 until all 8 bits if the Write-Enable command have been sent
  11. Pause for 5 cycles of CLK_P
  12. Set S#=1

These 12 steps could be coded using a VHDL state machine. 

When writing SPI communication HDL this way (and toggling CLK_SPI yourself), you should check that the steps with “Pause for 5 cycles of CLK_P” meet the serial timing shown in Fig 36 of the N25Q128A datasheet.  When this type of HDL meets timing, then it is said that you are “meeting timing by design” – which means that you don’t need to write any of the timing constraints for the SPI interface that you have shown to me.

N25Q128A_timing.jpg

View solution in original post

Tags (1)
10 Replies
Highlighted
863 Views
Registered: ‎01-22-2015

@jahnavijanu.y 

     Is it correct or do i need to change any pins?
I have checked the KC705 schematic dated 4-2-2012_15:15 and find that you have correctly identified all connections needed to control the N25Q128A flash.

You will need to create a clock and send it to input USRCCLKO of the STARTUPE2 primitive.  The STARTUPE2 primitive will send this clock to FPGA pin, B10, which connects to the clock pin of the N25Q128A flash.  The clock that you send to USRCCLKO need not be a real clock.  That is, it can simply be a signal that you toggle.

     As for reset i couldn't figure out how can i generate internally…
You can use the ICAPE2 primitive (UG953, pg374) to send an IPROG command which tells the FPGA to reconfigure itself from flash – see pages 145-146 of UG470(v1.13.1) for details.

     how can i check whether the data is passed into the flash successfully or not...
I recommend that you develop code for both write-to and read-from flash.  Then, you can verify a write-to flash by reading back what you have written.

Mark

0 Kudos
Highlighted
Contributor
Contributor
852 Views
Registered: ‎11-29-2019

Thank you for the reply,

I had written into the memory ,and readback from the memory device but it is in .mcs format and i am not getting how can i get the information about what is the data and which address it had stored? 

The process i followed is,

After i programmed the configuration memory device with .mcs ,i did erase,program,verify operations and i read back from the memory device and it is stored as .mcs file.

Thanks in advance,

Regards,

Jahnavi.

0 Kudos
Highlighted
826 Views
Registered: ‎01-22-2015

@jahnavijanu.y 

It is the .bin format file that you write to flash and not the .mcs format file.   I know this sounds confusing because we always prepare a .mcs file for flash memory.  However, software like iMPACT and Vivado convert the .mcs file to a .bin file before loading it into flash memory.bin_file.jpg

If you are not using multiboot (Chap 7 of UG470)  then you should write the .bin file into flash memory starting at address 0(zero).

0 Kudos
Highlighted
Contributor
Contributor
781 Views
Registered: ‎11-29-2019

Thank you for the reply,

I generated a bin file and i programmed it into the flash memory .

I had a code that will send write command,data,read command, how can i collect the output?

Thanks in advance,

Regards,

Jahnavi

0 Kudos
Highlighted
766 Views
Registered: ‎01-22-2015

@jahnavijanu.y 

Using hardware called an ethernet-to-RS232 converter, we send the bin file from a PC to the FPGA in consecutive 256 byte packets. The FPGA temporarily stores the packet in block-RAM (BRAM) until writing of the packet to flash is complete. The FPGA then tells the PC to send another packet. This process is repeated until the entire bin file is written to flash.

During read-back from flash, the process is reversed. That is, the FPGA reads blocks of 256 bytes from flash, temporarily stores each block of data in BRAM, and transmits each block of data to the PC via the RS232-to-ethernet converter.

In the PC, we compare the read-back data to the original bin file to verify that the bin file was correctly written to flash.

0 Kudos
Highlighted
Contributor
Contributor
723 Views
Registered: ‎11-29-2019

Thank you so much for the reply,

I now understand how the process is done inside the FPGA .

But i have a problem with qspi outline pins,...

I opened the hardware manager and and the dumped the program along with ila debug file.ltx but what i i found (in my program apb drives the inputs to the qspi ) the apb signals are coming correctly but when i tried checking the qspi dq0,dq1 pins it is showing either 1 or 0 continuosly ,so i have a doubt whether the data is going correctly from qspi lines to the flash or not.but in the simulation it worked fine.

I have a another doubt about the connection of startup2 primitive also as for the userclk i used my qspi output clk  is it correct? This clk will give clk pulses only when the data,address,cmd ...like some information is going and as for rest of time it is in 0 and doesn't toggle.

Thanks in advance,

Regards,

Jahnavi.

0 Kudos
Highlighted
696 Views
Registered: ‎01-22-2015

@jahnavijanu.y 

     ..with ila debug file.ltx but what i i found…
It is best if you probe signals with an oscilloscope.  This should be possible since the N25Q128A flash has an SO16 package on the KC705 board.  ILA can see only part of what is happening.

 

     …dq0,dq1 pins it is showing either 1 or 0 continuosly…
Please verify that your board is using the N25Q128A flash.  Then, carefully review the datasheet for this flash.  Note that this flash supports different communication protocols – two of which are extended SPI (SPIx1) and Quad-SPI (SPIx4).  Note that QSPI is an acronym for Queued-SPI, which is different from Quad-SPI. 

At power-up, the N25Q128A flash defaults to SPIx1 mode.  You may want to initially use SPIx1 for flash read/write since it is easiest.  Later, if you want to use Quad-SPI mode then you need to indicate this by writing to the flash Enhanced Volatile Configuration Register (see Table 14 in N25Q128A datasheet).

 

     I have a another doubt about the connection of startup2 primitive also as for the userclk i used my qspi output clk  is it correct? This clk will give clk pulses only when the data,address,cmd ...like some information is going and as for rest of time it is in 0 and doesn't toggle.
You must create the SPI clock and send it to STARTUPE2.USRCCLKO.  The SPI clock need not be a continuous clock.  That is, this clock can stop when you are not communicating with flash.  However, this clock, S#, and DQx lines need to toggle according to timing diagrams shown in the N25Q128A datasheet.

0 Kudos
Highlighted
Contributor
Contributor
646 Views
Registered: ‎11-29-2019

Thank you for the reply,

Yes,the kc705 board has N25Q128A flash.

I tried by using spi*1 and i changed the configuration.

I don't know how to probe the signals using oscilloscope.can you please  explain how can  i probe it?

Normally i used ila with different trigger points whether the data is going correctly in mosi line but the data is not as we expect.i.e, the spi_clk is generating 32 clk cycles(we defined only 8-clk pulses) which we never defined and the mosi line is completely 0( actually here a cmd has to pass). After that 8 spi_clk pulses are coming and the cmd is passing here.

I initially thought that there is a delay so that is why it is showing but after that again a 32-spi clk pulses are coming with mosi line as 0.and at the very large delay another data is passing. But in between spi_clk pulses are generating.

The constraints i used are,

set_property CONFIG_VOLTAGE 2.5 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]

set_property BITSTREAM.CONFIG.SPI_FALL_EDGE NO [current_design]
set_property CONFIG_MODE SPIx1 [current_design]
set_property IOSTANDARD LVDS [get_ports clk_p]
set_property PACKAGE_PIN AD12 [get_ports clk_p]
set_property IOSTANDARD LVCMOS25 [get_ports spi_csn_out_i]
set_property PACKAGE_PIN U19 [get_ports spi_csn_out_i]
set_property PACKAGE_PIN P24 [get_ports {spi_pad_data[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {spi_pad_data[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {spi_pad_data[1]}]
set_property PACKAGE_PIN P24 [get_ports {spi_pad_data[0]}]
set_property PACKAGE_PIN R25 [get_ports {spi_pad_data[1]}]
create_generated_clock -name cclk -source [get_pins STARTUPE2_inst/USRCCLKO] -combinational [get_pins STARTUPE2_inst/USRCCLKO]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets apb_clk]

// I am using clocking wizard to generate the clock i used a clk of 16 mhz, for my design.

Do i need to include these also?

set_clock_latency -min  0.5 [get_clocks cclk]
#set_clock_latency -max  6.7 [get_clocks cclk]
#set_input_delay -clock [get_clocks cclk] -clock_fall -min -add_delay 1.000 [get_ports {spi_pad_data[*]}]
#set_input_delay -clock [get_clocks cclk] -clock_fall -max -add_delay 6.000 [get_ports {spi_pad_data[*]}]
#set_output_delay -clock [get_clocks cclk] -min -add_delay -3.000 [get_ports {spi_pad_data[*]}]
#set_output_delay -clock [get_clocks cclk] -max -add_delay 2.000 [get_ports {spi_pad_data[*]}]
#set_output_delay -clock [get_clocks cclk] -min -add_delay -4.000 [get_ports spi_csn_out_i]
#set_output_delay -clock [get_clocks cclk] -max -add_delay 4.000 [get_ports spi_csn_out_i]

2) my another problem is when i programmed the flash ,it is saying dropping ila probes because it can't be found on programmed device. And the flash programming is successful.but ila is not working that .so in hardware manager i only programming the device and i am not doing programming the configuration memory.can i do that?

That means i can't use ila with programming of flash?. then how can i verify,that can be done by using oscilloscope?

Thanks in advance,

Regards,

Jahnavi.

 

 

0 Kudos
Highlighted
606 Views
Registered: ‎01-22-2015

@jahnavijanu.y 

An oscilloscope is electrical test equipment that allows you to probe and see electrical signals on your KC705 board.  If you don’t have one in your laboratory then maybe you can borrow one from the electrical technicians in your organization.

It appears that you have found software that does SPI communication and you are trying to make sense of it.  However, SPI communication is quite simple.  You may find it easier to develop your own SPI communication software(HDL) rather than trying to understand someone else’s software. 

If you want to develop your own SPI communication HDL, then I recommend you treat the SPI clock, CLK_SPI, as an ordinary signal – and not generate it using the clocking wizard.  I will show you what I mean later.  Next, use the clocking wizard to create a fast pacing clock, CLK_P. 

The 12 steps below shown how your own HDL (in SPIx1 mode) might work for the N25Q128A “Write Enable” command, when CLK_P=100MHz and CLK_SPI=C=10MHz.

N25Q128A_write_enable.jpg

  1. Set CLK_SPI=C=1. Set S#=1.  <<note how CLK_SPI is assigned values in the same way you assign values to S#
  2. Pause for 5 cycles of CLK_P  <<note that 10 cycles of CLK_P is equal to one cycle of CLK_SPI
  3. Set S#=0
  4. Pause for 5 cycles of CLK_P
  5. Simultaneously set DQ0=0 and set CLK_SPI=0
  6. Pause for 5 cycles of CLK_P
  7. Set CLK_SPI=1
  8. Pause for 5 cycles of CLK_P
  9. Simultaneously place another bit value on DQ0 and set CLK_SPI=0
  10. Repeat steps 6-9 until all 8 bits if the Write-Enable command have been sent
  11. Pause for 5 cycles of CLK_P
  12. Set S#=1

These 12 steps could be coded using a VHDL state machine. 

When writing SPI communication HDL this way (and toggling CLK_SPI yourself), you should check that the steps with “Pause for 5 cycles of CLK_P” meet the serial timing shown in Fig 36 of the N25Q128A datasheet.  When this type of HDL meets timing, then it is said that you are “meeting timing by design” – which means that you don’t need to write any of the timing constraints for the SPI interface that you have shown to me.

N25Q128A_timing.jpg

View solution in original post

Tags (1)
Highlighted
Contributor
Contributor
547 Views
Registered: ‎11-29-2019

Thank you so much for the reply.

 

0 Kudos