08-08-2020 01:14 AM
How can I simulate a RISC V Core and its extensions?
I have been given a task by my professor to simulate the BitManip extensions of the RISC V Core for a Computer Vision project.
Here is the reference paper he provided me:
Can anybody guide me through the process?
08-09-2020 07:27 PM
As someone who has built their own CPU, it really depends. It depends upon the CPU. It depends upon its capabilities. Sorry, but RISC-V isn't quite specific enough to answer those questions. You might need to look into the specific CPU's implementation.
In my case, when I simulate the ZipCPU (my own creation), I have to simulate an entire ecosystem as well. I'm therefore simulating the CPU, serial port, flash memory, and sometimes more--SD card, video, ethernet, you name it. I've posted many of these simulations on github, and discussed most of them on my blog at zipcpu.com. For example, here is a design containing at first a ZipCPU but now/finally a PicoRV32 RISC-V CPU.
Most of my simulations these days have one of two modes.
When booting from the SD-Card, I typically point the simulation at a file to use as an SD-Card disk. The simulation then reads and writes to that "disk" as the CPU wants it to. Sure, it's slow, but it works. When I'm not running the simulation, I can then "mount" the SD card onto my system using Linux loop-back mode and adjust any files on it as necessary.
I've done most of my simulation work to date using Verilator. I imagine Vivado has some simulation capabilities built in, but most of my board simulation requirements are for C/C++ models not RTL models and ... I haven't (yet) figured out how (or if) Vivado supports integrating C/C++ simulation models to even try that approach. To date, therefore, Verilator has met my needs quite well.