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Participant
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Registered: ‎12-07-2008

Re: spartan 6 bit stream download failure

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followed is the value when I read device statue manually:

INFO:iMPACT - Current time: 2018/8/29 18:11:02
Maximum TCK operating frequency for this device chain: 15000000.
Validating chain...
Boundary-scan chain validated successfully.
'2': Reading bootsts register contents...
[0] VALID_0 - ERROR OR END OF STARTUP (EOS) DETECTED : 0
[1] FALLBACK_0 - FALLBACK RECONFIGURATION ATTEMPT DETECTED : 0
[2] RESERVED : 0
[3] WTO_ERROR_0 - WATCHDOG TIME OUT ERROR : 0
[4] ID_ERROR_0 - FPGA DEVICE IDCODE ERROR : 0
[5] CRC_ERROR_0 - CYCLIC REDUNDANCY CHECK (CRC) ERROR : 0
[6] VALID_1 - ERROR OR END OF STARTUP (EOS) DETECTED : 0
[7] FALLBACK_1 - FALLBACK RECONFIGURATION ATTEMPT DETECTED : 0
[8] RESERVED : 0
[9] WTO_ERROR_1 - WATCHDOG TIME OUT ERROR : 0
[10] ID_ERROR_1 - FPGA DEVICE IDCODE ERROR : 0
[11] CRC_ERROR_1 - CYCLIC REDUNDANCY CHECK (CRC) ERROR : 0
[12] STRIKE CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[13] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[14] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[15] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
'2': Reading status register contents...
[0] CRC ERROR : 0
[1] IDCODE ERROR : 0
[2] DCM LOCK STATUS : 1
[3] GTS_CFG_B STATUS : 0
[4] GWE STATUS : 0
[5] GHIGH STATUS : 0
[6] DECRYPTION ERROR : 0
[7] DECRYPTOR ENABLE : 0
[8] HSWAPEN PIN : 0
[9] MODE PIN M[0] : 1
[10] MODE PIN M[1] : 0
[11] RESERVED : 0
[12] INIT_B PIN : 0
[13] DONE PIN : 0
[14] SUSPEND STATUS : 0
[15] FALLBACK STATUS : 1

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Participant
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Registered: ‎12-07-2008

Re: spartan 6 bit stream download failure

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This problem is soloved, as given in another post.

View solution in original post

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Explorer
Explorer
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Registered: ‎05-08-2018

Re: spartan 6 bit stream download failure

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What did the DONE pin do?

 

What did the INIT_b pin do?

 

Looks like it is working.  Why do you think it is failing?  Maybe it is doing exactly what you programmed it to do? 

 

Remember, you may have made a mistake in your verilog/VHDL.  Did you run a test bench to verify your design?

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Registered: ‎12-07-2008

Re: spartan 6 bit stream download failure

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Hi alesea,

thanks for your reply. This topic is supposed to be a reply to my question in the following topic:

https://forums.xilinx.com/t5/Design-Tools-Others/spartan-6-bit-stream-download-failure/m-p/885728

But I don't know why it appears here.

My problem is that I can download a simple breathing LED project to my Spartan 6 every time; but if  I add some other logics into my project (DCM, selectIo, IBUF, OBUF), then the configuration process acts like randomly.

the device statue register values appears to be incorrect, and to some degree random after each configuration process; but they seem to be correct if I read them manually.

Please see the linked topic above. thank you!

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Explorer
Explorer
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Registered: ‎05-08-2018

Re: spartan 6 bit stream download failure

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OK,

 

This is a pcb designed by you.  The design that works, is it programmed over JTAG?  If you program ten times, is it OK every time?

 

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Participant
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Registered: ‎12-07-2008

Re: spartan 6 bit stream download failure

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yes, that design will work every time.

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Participant
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Registered: ‎12-07-2008

Re: spartan 6 bit stream download failure

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I have made some modifications to the design that didn't work, and it seems that the DCM module made the difference, but this needs to be confirmed.
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Participant
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Registered: ‎12-07-2008

Re: spartan 6 bit stream download failure

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This problem is soloved, as given in another post.

View solution in original post

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